log mbist short

reads the domains xml files

in xml files we will have domains masking, domains lists in the below format
d={1 {}} r=1 n=1 c=1 j=0 j=1
it also defines

DomainMaskList before: {1 {}}
DomainMaskList after: {1 {}}

Then calculates the debug wait cycles

INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0XAL: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: --------------------------------------------------
INFO_MBIST: DEBUG_WAIT_CYCLE: Total Me_Cnt (finalMe:5- initMe:4) : 2
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL_write cycles : 5376
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL_read cycles : 2688
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL cycles : 8064
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_SP_MUL cycles : 296
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_PDP_MUL cycles : 43048
INFO_MBIST: Calculated waitcycle for region_inst : shxs0xal is 44098

As below
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0XTQ: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0XPL: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0LNK1: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0LNK0: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0LNKM: masked domain List inside wait_cycle_calculation:

Summary of results

INFO_MBIST: INFO used in wait_cycle calculation : design_type :rtl
INFO_MBIST: INFO used in wait_cycle calculation : clock_mode :jtag_bypass
INFO_MBIST: INFO used in wait_cycle calculation : chiplet_inst : SHX_S0
INFO_MBIST: INFO used in wait_cycle calculation : jtag_freq : 200
INFO_MBIST: INFO used in wait_cycle calculation : subtest : Short
INFO_MBIST: waitCycles required to complete all chiplets :50242

then the programing config begis to shift chains

shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/TOP_FS, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/TOP_FS

It will begin to shift data to following below jtag register
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/JTAG_FUSE_CTRL

Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/CHIPLET_LOGIC
Shifting data to jtag registers: s0_0/testmaster/I1500_CHAIN_CTRL
Shifting data to jtag registers: t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_CTL
Shifting data to jtag registers: s0_0/testmaster/I1500_CHAIN_CTRL
Shifting data to jtag registers: t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_DATA_mbist_sts
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_CTL

after shifting values to the register I1500_CHAIN_CTRL we are making
"s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON
for S0_0 broad cast is ON , t0_0 Broadcast is OFF

for some programing we are making ON/OFF broadcast i dont know

# clear out prgmConfig values at the end of mbist API because when we are doing broadcast we have used jtagConfig to shift in value in to register
$prgmConfig clear_program_value

Then after
INFO: ramList_1_0 doesn't exist
INFO: ramList_1_1 doesn't exist
INFO: ramList_1_2 doesn't exist
INFO: ramList_1_3 doesn't exist
INFO: ramList_1_4 doesn't exist
INFO: ramList_1_5 doesn't exist

------>>

INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/MBIST_TOP, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

INFO_MBIST: Waiting 50242 Cycles for MBIST test to complete...
(INFO:VEC_378) Cycle Info: wait_cycles (start@29343, end@79584) = 50242 cycles. Accumulated 50533 cycles.
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is serial
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass region_without_mbist =
INFO_MBIST: DEBUG_BROADCAST: regions in bypass
INFO_MBIST: DEBUG_BROADCAST: regions in serial 0 1 2 3 4 5

) jtagConfig property "enable_dr_programming_log" is off, all status of shift_dr registers will be removed when programming Jtag registers

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 79585 shift_ir 28(24____) 058905____
cycle 79619 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_453B) jtagConfig property "enable_dr_programming_log" is on, all shift_dr register status will be logged when programming
INFO_MBIST: Scanning out results from central MBIST chain for chiplet s0_0(SHX_S0)...
INFO: ramList_1_0 doesn't exist
INFO: ramList_1_1 doesn't exist
INFO: ramList_1_2 doesn't exist
INFO: ramList_1_3 doesn't exist
INFO: ramList_1_4 doesn't exist
INFO: ramList_1_5 doesn't exist

##################
INFO: executing SubTest INIT Sequence ...
(INFO:VEC_378) Cycle Info: wait_cycles (start@27241, end@27359) = 119 cycles. Accumulated 290 cycles.
(INFO:AFU_057) In label 'SUBTEST_INIT_END' dump signature 'V0_10342'
(INFO:VEC_378) Cycle Info: wait_cycles (start@27360, end@27360) = 1 cycles. Accumulated 291 cycles.
INFO: executing API: ::ATE::mbist::Short -prgmConfig $prgmConfig -testConfig $testConfig -chipletId 1
INFO: Reading Xml Files...
INFO_MBIST: MBIST Masking domains d={1 {}} r=1 n=1 c=1 j=0 j=1
INFO_MBIST: DomainMaskList before: {1 {}}
INFO_MBIST: DomainMaskList after: {1 {}}
INFO_MBIST: DEBUG_WAIT_CYCLE: --------------------------------------------------
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0XAL: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: --------------------------------------------------
INFO_MBIST: DEBUG_WAIT_CYCLE: Total Me_Cnt (finalMe:5- initMe:4) : 2
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL_write cycles : 5376
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL_read cycles : 2688
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL cycles : 8064
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_SP_MUL cycles : 296
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_PDP_MUL cycles : 43048

INFO_MBIST: Calculated waitcycle for region_inst : shxs0lnkm is 46146

INFO_MBIST: INFO used in wait_cycle calculation : design_type :rtl

INFO_MBIST: INFO used in wait_cycle calculation : clock_mode :jtag_bypass

INFO_MBIST: INFO used in wait_cycle calculation : chiplet_inst : SHX_S0

INFO_MBIST: INFO used in wait_cycle calculation : jtag_freq : 200

INFO_MBIST: INFO used in wait_cycle calculation : subtest : Short

INFO_MBIST: waitCycles required to complete all chiplets :50242

INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 27361. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/TOP_FS, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 27361 shift_ir 28(24____) 052405____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/TOP_FS
cycle 27395 shift_dr 46(42____) 00000000000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 27450. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/JTAG_FUSE_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 27450 shift_ir 28(24____) 052f05____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/JTAG_FUSE_CTRL
cycle 27484 shift_dr 143(139____) 3c000000000000000000000000000000000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 27632. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/CHIPLET_LOGIC, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 27632 shift_ir 28(24____) 052605____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/CHIPLET_LOGIC
cycle 27666 shift_dr 500(496____) 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28175. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/I1500_CHAIN_CTRL, s0_0/SHX_S0_1500_wrapper/WS_BYPASS, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28175 shift_ir 28(24____) 890505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/testmaster/I1500_CHAIN_CTRL
cycle 28209 shift_dr 9(5____) 10____
expected XXXXX____
(INFO:VEC_301) Cycle 28218 ChainIndex=6 shift register "s0_0/testmaster/testmaster_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28220 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/testmaster/testmaster_cli_inst" : BROADCAST = ON.
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28223. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/WS_BYPASS, t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
cycle 28223 shift_ir 28(24____) 050589____
(INFO:VEC_232) Shifting data to jtag registers: t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
cycle 28257 shift_dr 9(5____) 04____
expected XXXXX____
(INFO:VEC_301) Cycle 28264 ChainIndex=4 shift register "t0_0/SHX_T0_1500_wrapper/shxt0pads0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28266 ChainIndex=6 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "t0_0/SHX_T0_1500_wrapper/shxt0pads0_cli_inst" : BROADCAST = ON.
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28271. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28271 shift_ir 28(24____) 058905____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL

expected XXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 28314 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28316 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 28317 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28319 ChainIndex=11 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 28320 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28322 ChainIndex=14 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 28323 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28325 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 28326 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28328 ChainIndex=20 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 28329 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28331 ChainIndex=23 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON.
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28339. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_CTL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28339 shift_ir 28(24____) 051505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_CTL
cycle 28373 shift_dr 19(15____) 0000____
expected XXXXXXXXXXXXXXX____
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28401. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/I1500_CHAIN_CTRL, s0_0/SHX_S0_1500_wrapper/WS_BYPASS, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28401 shift_ir 28(24____) 890505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/testmaster/I1500_CHAIN_CTRL
cycle 28435 shift_dr 9(5____
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_CTL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28339 shift_ir 28(24____) 051505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_CTL
cycle 28373 shift_dr 19(15____) 0000____
expected XXXXXXXXXXXXXXX____
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28401. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/I1500_CHAIN_CTRL, s0_0/SHX_S0_1500_wrapper/WS_BYPASS, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28401 shift_ir 28(24____) 890505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/testmaster/I1500_CHAIN_CTRL
cycle 28435 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_301) Cycle 28444 ChainIndex=6 shift register "s0_0/testmaster/testmaster_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28446 ChainIndex=8 Programming value 1'h1 --> 1'h0 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/testmaster/testmaster_cli_inst" : BROADCAST = OFF.
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28449. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/WS_BYPASS, t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
cycle 28449 shift_ir 28(24____) 050589____
(INFO:VEC_232) Shifting data to jtag registers: t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
cycle 28483 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_301) Cycle 28490 ChainIndex=4 shift register "t0_0/SHX_T0_1500_wrapper/shxt0pads0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28492 ChainIndex=6 Programming value 1'h1 --> 1'h0 for field="broadcast_write"
(INFO:VEC_365) Client "t0_0/SHX_T0_1500_wrapper/shxt0pads0_cli_inst" : BROADCAST = OFF.
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28497. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28497 shift_ir 28(24____) 058905____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL

expected XXXXXXXXXXXXXXXXXXXXX____

(INFO:VEC_301) Cycle 28540 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28542 ChainIndex=8 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_301) Cycle 28543 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28545 ChainIndex=11 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_301) Cycle 28546 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28548 ChainIndex=14 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_301) Cycle 28549 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28551 ChainIndex=17 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_301) Cycle 28552 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28554 ChainIndex=20 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_301) Cycle 28555 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28557 ChainIndex=23 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = OFF.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = OFF.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = OFF.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = OFF.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = OFF.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = OFF.

INFO_MBIST: asserting mbist_ramaccess_rst_ 1

INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on

INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 28565 shift_ir 28(24____) 058905____

(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL

cycle 28599 shift_dr 25(21____) 092490____

expected XXXXXXXXXXXXXXXXXXXXX____

INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 28565 shift_ir 28(24____) 058905____

(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL

cycle 28599 shift_dr 25(21____) 092490____

expected XXXXXXXXXXXXXXXXXXXXX____

(INFO:VEC_301) Cycle 28608 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28610 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_301) Cycle 28611 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28613 ChainIndex=11 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_301) Cycle 28614 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28616 ChainIndex=14 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_301) Cycle 28617 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28619 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_301) Cycle 28620 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28622 ChainIndex=20 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_301) Cycle 28623 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28625 ChainIndex=23 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON.

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 28629 shift_ir 28(24____) 051a05____

(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL

cycle 28663 shift_dr 32(28____) 0000000____

expected XXXXXXXXXXXXXXXXXXXXXXXXXXXX____

(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared

(INFO:VEC_379) Cycle Info: move_to_state (start@28700, end@28749) = 50 cycles. Accumulated 50 cycles (end state = RUN_TEST_IDLE, the number of TCK cycles stay on end state = 50).

INFO_MBIST: desserting mbist_ramaccess_rst_

INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on

INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 28750 shift_ir 28(24____) 051a05____

(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL

cycle 28784 shift_dr 32(28____) 0002000____

expected XXXXXXXXXXXXXXXXXXXXXXXXXXXX____

(INFO:VEC_301) Cycle 28793 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/RAM_ACCESS_CTRL"

(INFO:VEC_300A) Cycle 28804 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="u0/mbist_ramaccess_rst_"

(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared

(INFO:VEC_379) Cycle Info: move_to_state (start@28821, end@28870) = 50 cycles. Accumulated 100 cycles (end state = RUN_TEST_IDLE, the number of TCK cycles stay on end state = 50).

INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on

INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/MBIST_TOP, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 28871 shift_ir 28(24____) 051605____

(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP

cycle 28905 shift_dr 197(193____) 0000000000000000000000000000000000000000000000008____

expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____

(INFO:VEC_301) Cycle 28914 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/MBIST_TOP"

(INFO:VEC_300A) Cycle 28915 ChainIndex=7 Programming value 1'h0 --> 1'h1 for field="u0/start_bits"

(INFO:VEC_300A) Cycle 28938 ChainIndex=30 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"

(INFO:VEC_300A) Cycle 28939 ChainIndex=31 Programming value 30'h3fffffff --> 30'h00000000 for field="u0/bist_mask_bits"

(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared

INFO: ramList_1_0 doesn't exist

INFO: ramList_1_1 doesn't exist

INFO: ramList_1_2 doesn't exist

INFO: ramList_1_3 doesn't exist

INFO: ramList_1_4 doesn't exist

INFO: ramList_1_5 doesn't exist

INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on

INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/MBIST_TOP, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 29107 shift_ir 28(24____) 051605____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
cycle 29141 shift_dr 197(193____) 0000000000000000000000000000000000000000004814118____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 29150 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 29152 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 29154 ChainIndex=10 Programming value 8'h00 --> 8'h04 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 29162 ChainIndex=18 Programming value 8'h00 --> 8'h05 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 29171 ChainIndex=27 Programming value 1'h0 --> 1'h1 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 29174 ChainIndex=30 Programming value 1'h0 --> 1'h1 for field="u0/bist_mask_sel_bits"
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: Waiting 50242 Cycles for MBIST test to complete...
(INFO:VEC_378) Cycle Info: wait_cycles (start@29343, end@79584) = 50242 cycles. Accumulated 50533 cycles.
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is serial
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass region_without_mbist =
INFO_MBIST: DEBUG_BROADCAST: regions in bypass
INFO_MBIST: DEBUG_BROADCAST: regions in serial 0 1 2 3 4 5
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = OFF.
(WARN:VEC_453A) jtagConfig property "enable_dr_programming_log" is off, all status of shift_dr registers will be removed when programming Jtag registers
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 79585 shift_ir 28(24____) 058905____
cycle 79619 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_453B) jtagConfig property "enable_dr_programming_log" is on, all shift_dr register status will be logged when programming
INFO_MBIST: Scanning out results from central MBIST chain for chiplet s0_0(SHX_S0)...
INFO: ramList_1_0 doesn't exist
INFO: ramList_1_1 doesn't exist
INFO: ramList_1_2 doesn't exist
INFO: ramList_1_3 doesn't exist
INFO: ramList_1_4 doesn't exist
INFO: ramList_1_5 doesn't exist
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 79633. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/MBIST_TOP, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 79633 shift_ir 28(24____) 051605____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
cycle 79667 shift_dr 1147(1143____) 00000000000000000000000000000000000000000000000a0000000000000000000000000000000000000000000000280000000000000000000000000000000000000000000000a0000000000000000000000000000000000000000000000280000000000000000000000000000000000000000000000a000000000000000000000000000000000000000000000028____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXX____
(INFO:VEC_301) Cycle 79676 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 79678 ChainIndex=8 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 79679 ChainIndex=9 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 79680 ChainIndex=10 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 79688 ChainIndex=18 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 79697 ChainIndex=27 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 79700 ChainIndex=30 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
(INFO:VEC_301) Cycle 79866 ChainIndex=196 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 79868 ChainIndex=198 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 79869 ChainIndex=199 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 79870 ChainIndex=200 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 79878 ChainIndex=208 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 79887 ChainIndex=217 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 79890 ChainIndex=220 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
(INFO:VEC_301) Cycle 80056 ChainIndex=386 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 80058 ChainIndex=388 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 80059 ChainIndex=389 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 80060 ChainIndex=390 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 80068 ChainIndex=398 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 80077 ChainIndex=407 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 80080 ChainIndex=410 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
(INFO:VEC_301) Cycle 80246 ChainIndex=576 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 80248 ChainIndex=578 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 80249 ChainIndex=579 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 80250 ChainIndex=580 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 80258 ChainIndex=588 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 80267 ChainIndex=597 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 80270 ChainIndex=600 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
(INFO:VEC_301) Cycle 80436 ChainIndex=766 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 80438 ChainIndex=768 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 80439 ChainIndex=769 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 80440 ChainIndex=770 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 80448 ChainIndex=778 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 80457 ChainIndex=787 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 80460 ChainIndex=790 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
(INFO:VEC_301) Cycle 80626 ChainIndex=956 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 80628 ChainIndex=958 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 80629 ChainIndex=959 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 80630 ChainIndex=960 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 80638 ChainIndex=968 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 80647 ChainIndex=977 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 80650 ChainIndex=980 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
INFO_MBIST: Select chain daisy_mbist_status_chain for clusterInst SHX_S0_1500_wrapper
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 80823 shift_ir 28(24____) 058905____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
cycle 80857 shift_dr 25(21____) 092490____
expected XXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 80866 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80868 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 80869 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80871 ChainIndex=11 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 80872 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80874 ChainIndex=14 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 80875 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80877 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 80878 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80880 ChainIndex=20 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 80881 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80883 ChainIndex=23 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON.
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 80887 shift_ir 28(24____) 051a05____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
cycle 80921 shift_dr 32(28____) 4063fe0____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 80930 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/RAM_ACCESS_CTRL"
(INFO:VEC_300A) Cycle 80931 ChainIndex=7 Programming value 10'h000 --> 10'h3fc for field="u0/chain_sel"
(INFO:VEC_300A) Cycle 80945 ChainIndex=21 Programming value 1'h0 --> 1'h1 for field="u0/clk_switch_en"
(INFO:VEC_300A) Cycle 80946 ChainIndex=22 Programming value 1'h0 --> 1'h1 for field="u0/shift_only"
(INFO:VEC_300A) Cycle 80954 ChainIndex=30 Programming value 1'h0 --> 1'h1 for field="u0/debug_on"
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is serial
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass region_without_mbist =
INFO_MBIST: DEBUG_BROADCAST: regions in bypass
INFO_MBIST: DEBUG_BROADCAST: regions in serial 0 1 2 3 4 5
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = OFF.
(WARN:VEC_453A) jtagConfig property "enable_dr_programming_log" is off, all status of shift_dr registers will be removed when programming Jtag registers
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 80958 shift_ir 28(24____) 058905____
cycle 80992 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_453B) jtagConfig property "enable_dr_programming_log" is on, all shift_dr register status will be logged when programming
INFO_MBIST: Scanning out local mbist status chain for SHX_S0_1500_wrapper
INFO: ramList_1_0 doesn't exist
INFO: ramList_1_1 doesn't exist
INFO: ramList_1_2 doesn't exist
INFO: ramList_1_3 doesn't exist
INFO: ramList_1_4 doesn't exist
INFO: ramList_1_5 doesn't exist
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 81006. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_DATA_mbist_sts, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 81006 shift_ir 28(24____) 050d05____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_DATA_mbist_sts
cycle 81040 shift_dr 7653(7649____) 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000X00000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000X000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000X000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000X00000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000X00000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000X00000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000X000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000000X0000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000000X0000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000000X0000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000000X0000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000X00000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000X00000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000X00000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXX____
INFO_MBIST: Deasserting debug mode for configIndex 1
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 88702 shift_ir 28(24____) 058905____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
cycle 88736 shift_dr 25(21____) 092490____
expected XXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 88745 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88747 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88748 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88750 ChainIndex=11 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88751 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88753 ChainIndex=14 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88754 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88756 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88757 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88759 ChainIndex=20 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88760 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88762 ChainIndex=23 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON.
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 88766 shift_ir 28(24____) 051a05____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
cycle 88800 shift_dr 32(28____) 0002000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 88809 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/RAM_ACCESS_CTRL"
(INFO:VEC_300A) Cycle 88810 ChainIndex=7 Programming value 10'h3fc --> 10'h000 for field="u0/chain_sel"
(INFO:VEC_300A) Cycle 88824 ChainIndex=21 Programming value 1'h1 --> 1'h0 for field="u0/clk_switch_en"
(INFO:VEC_300A) Cycle 88825 ChainIndex=22 Programming value 1'h1 --> 1'h0 for field="u0/shift_only"
(INFO:VEC_300A) Cycle 88833 ChainIndex=30 Programming value 1'h1 --> 1'h0 for field="u0/debug_on"
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is serial
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass region_without_mbist =
INFO_MBIST: DEBUG_BROADCAST: regions in bypass
INFO_MBIST: DEBUG_BROADCAST: regions in serial 0 1 2 3 4 5
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = OFF.
(WARN:VEC_453A) jtagConfig property "enable_dr_programming_log" is off, all status of shift_dr registers will be removed when programming Jtag registers
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 88837 shift_ir 28(24____) 058905____
cycle 88871 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_453B) jtagConfig property "enable_dr_programming_log" is on, all shift_dr register status will be logged when programming
INFO_MBIST: clearing out registers
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 88885 shift_ir 28(24____) 058905____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
cycle 88919 shift_dr 25(21____) 092490____
expected XXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 88928 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88930 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88931 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88933 ChainIndex=11 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88934 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88936 ChainIndex=14 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88937 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88939 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88940 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88942 ChainIndex=20 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88943 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88945 ChainIndex=23 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON.
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/MBIST_TOP, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 88949 shift_ir 28(24____) 051605____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
cycle 88983 shift_dr 197(193____) 0000000000000000000000000000000000000000000000000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 88992 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 88993 ChainIndex=7 Programming value 1'h1 --> 1'h0 for field="u0/start_bits"
(INFO:VEC_300A) Cycle 88995 ChainIndex=9 Programming value 1'h1 --> 1'h0 for field="u0/done_bits"
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_CTL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 89185 shift_ir 28(24____) 051505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_CTL
cycle 89219 shift_dr 19(15____) 0100____
expected XXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 89228 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/RAM_CTL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/RAM_CTL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/RAM_CTL", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/RAM_CTL", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/RAM_CTL", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/RAM_CTL"
(INFO:VEC_300A) Cycle 89234 ChainIndex=12 Programming value 1'h0 --> 1'h1 for field="u0/write_inh"
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is serial
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass region_without_mbist =
INFO_MBIST: DEBUG_BROADCAST: regions in bypass
INFO_MBIST: DEBUG_BROADCAST: regions in serial 0 1 2 3 4 5
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = OFF.
(WARN:VEC_453A) jtagConfig property "enable_dr_programming_log" is off, all status of shift_dr registers will be removed when programming Jtag registers
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 89243 shift_ir 28(24____) 058905____
cycle 89277 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_453B) jtagConfig property "enable_dr_programming_log" is on, all shift_dr register status will be logged when programming
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: Moving to RTI state
JTAG init to state: RTI
(INFO:VEC_379) Cycle Info: move_to_state (start@89291, end@89300) = 10 cycles. Accumulated 110 cycles (end state = RUN_TEST_IDLE, the number of TCK cycles stay on end state = 10).
(INFO:ATE_105) procedure '::ATE::mbist::Short' execute time is: 38 mins 48 secs

INFO: executing Global EOT Sequence ...
(INFO:VEC_378) Cycle Info: wait_cycles (start@89301, end@89399) = 99 cycles. Accumulated 50632 cycles.
(INFO:AFU_057) In label 'EOT_BEGIN' dump signature 'V0_40996'
(INFO:VEC_378) Cycle Info: wait_cycles (start@89400, end@89400) = 1 cycles. Accumulated 50633 cycles.
(INFO:ATE_109) 05/04/2020 10:59:58 starting global eot sequence 'BreakPoint Start_UPHY_Power_Off' @cycle 89401
(INFO:VEC_378) Cycle Info: wait_cycles (start@89401, end@89519) = 119 cycles. Accumulated 50752 cycles.
(INFO:AFU_057) In label 'Start_UPHY_Power_Off' dump signature 'V0_34450'
(INFO:VEC_378) Cycle Info: wait_cycles (start@89520, end@89520) = 1 cycles. Accumulated 50753 cycles.
(INFO:ATE_109) 05/04/2020 11:00:03 starting global eot sequence 'UPHY_Power_Off' @cycle 89521
05/04/2020 11:00:03==============@cycle 89521 ENTER procedure: ::UPHY_Power_Off==============
test_name is: mbist.mbist
subtest_name is: Short
design_type is: rtl
design_scope is: FULLCHIP
clock_mode is : jtag_bypass
sub_clock_mode is :
init modes: extest 0 testclk_trigger 0 tam 0 xtr 0 intest 0 serdesclk_trigger 0 fabric_pex 0 stuckat 0 ftm 0
sub_modes is:
ATE_config is:
UPHY PowerDown Sequence Enabled
05/04/2020 11:00:03==============@cycle 89521 LEAVE procedure: ::UPHY_Power_Off==============
(INFO:ATE_105) procedure '::UPHY_Power_Off' execute time is: 1 secs
(INFO:ATE_109) 05/04/2020 11:00:03 starting global eot sequence 'BreakPoint End_UPHY_Power_Off' @cycle 89521
(INFO:VEC_378) Cycle Info: wait_cycles (start@89521, end@89639) = 119 cycles. Accumulated 50872 cycles.
(INFO:AFU_057) In label 'End_UPHY_Power_Off' dump signature 'V0_35614'
(INFO:VEC_378) Cycle Info: wait_cycles (start@89640, end@89640) = 1 cycles. Accumulated 50873 cycles.
(INFO:VEC_378) Cycle Info: wait_cycles (start@89641, end@89759) = 119 cycles. Accumulated 50992 cycles.
(INFO:AFU_057) In label 'GLOBAL_EOT_END' dump signature 'V0_57754'
(INFO:VEC_378) Cycle Info: wait_cycles (start@89760, end@89760) = 1 cycles. Accumulated 50993 cycles.

INFO: executing Test EOT Sequence ...
(INFO:VEC_378) Cycle Info: wait_cycles (start@89761, end@89879) = 119 cycles. Accumulated 51112 cycles.
(INFO:AFU_057) In label 'TEST_EOT_END' dump signature 'V0_1325'
(INFO:VEC_378) Cycle Info: wait_cycles (start@89880, end@89880) = 1 cycles. Accumulated 51113 cycles.

INFO: executing SubTest EOT Sequence ...
(INFO:VEC_378) Cycle Info: wait_cycles (start@89881, end@89999) = 119 cycles. Accumulated 51232 cycles.
(INFO:AFU_057) In label 'SUBTEST_EOT_END' dump signature 'V0_55232'
(INFO:VEC_378) Cycle Info: wait_cycles (start@90000, end@90000) = 1 cycles. Accumulated 51233 cycles.
(INFO:VEC_313) TN->PLI: force tb.TB_sim_run 0 0 0
(INFO:VEC_378) Cycle Info: wait_cycles (start@90001, end@90001) = 1 cycles. Accumulated 51234 cycles.
(INFO:VEC_378) Cycle Info: wait_cycles (start@90002, end@90119) = 118 cycles. Accumulated 51352 cycles.
(INFO:AFU_057) In label 'END_OF_TEST' dump signature 'V0_7439'
(INFO:VEC_378) Cycle Info: wait_cycles (start@90120, end@90120) = 1 cycles. Accumulated 51353 cycles.
(INFO:AFU_061) Summary Disable Event Num: 2
(INFO:AFU_061) Summary Total Event Num: 136
normalCycleCount: 90121
###################################
# dft programming modes summary #
###################################
dft programming mode:
N/A

dft programming common modes:
s0_0: N/A
t0_0: N/A

Lyte Byte Tech News

Friday 15 May 2020

log mbist short

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