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Friday 15 May 2020

log mbist short

Display API 12:34 No comments

reads the domains xml files

in xml files we will have domains masking, domains lists in the below format
d={1 {}} r=1 n=1 c=1 j=0 j=1
it also defines

DomainMaskList before: {1 {}}
DomainMaskList after: {1 {}}

Then calculates the debug wait cycles

INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0XAL: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: --------------------------------------------------
INFO_MBIST: DEBUG_WAIT_CYCLE: Total Me_Cnt (finalMe:5- initMe:4) : 2
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL_write cycles : 5376
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL_read cycles : 2688
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL cycles : 8064
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_SP_MUL cycles : 296
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_PDP_MUL cycles : 43048
INFO_MBIST: Calculated waitcycle for region_inst : shxs0xal is 44098

As below
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0XTQ: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0XPL: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0LNK1: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0LNK0: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0LNKM: masked domain List inside wait_cycle_calculation:

Summary of results

INFO_MBIST: INFO used in wait_cycle calculation : design_type :rtl
INFO_MBIST: INFO used in wait_cycle calculation : clock_mode :jtag_bypass
INFO_MBIST: INFO used in wait_cycle calculation : chiplet_inst : SHX_S0
INFO_MBIST: INFO used in wait_cycle calculation : jtag_freq : 200
INFO_MBIST: INFO used in wait_cycle calculation : subtest : Short
INFO_MBIST: waitCycles required to complete all chiplets :50242

then the programing config begis to shift chains

shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/TOP_FS, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/TOP_FS

It will begin to shift data to following below jtag register
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/JTAG_FUSE_CTRL

Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/CHIPLET_LOGIC
Shifting data to jtag registers: s0_0/testmaster/I1500_CHAIN_CTRL
Shifting data to jtag registers: t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_CTL
Shifting data to jtag registers: s0_0/testmaster/I1500_CHAIN_CTRL
Shifting data to jtag registers: t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_DATA_mbist_sts
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_CTL

after shifting values to the register I1500_CHAIN_CTRL we are making
"s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON
for S0_0 broad cast is ON , t0_0 Broadcast is OFF

for some programing we are making ON/OFF broadcast i dont know

# clear out prgmConfig values at the end of mbist API because when we are doing broadcast we have used jtagConfig to shift in value in to register
$prgmConfig clear_program_value

Then after
INFO: ramList_1_0 doesn't exist
INFO: ramList_1_1 doesn't exist
INFO: ramList_1_2 doesn't exist
INFO: ramList_1_3 doesn't exist
INFO: ramList_1_4 doesn't exist
INFO: ramList_1_5 doesn't exist

------>>

INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/MBIST_TOP, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

INFO_MBIST: Waiting 50242 Cycles for MBIST test to complete...
(INFO:VEC_378) Cycle Info: wait_cycles (start@29343, end@79584) = 50242 cycles. Accumulated 50533 cycles.
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is serial
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass region_without_mbist =
INFO_MBIST: DEBUG_BROADCAST: regions in bypass
INFO_MBIST: DEBUG_BROADCAST: regions in serial 0 1 2 3 4 5

) jtagConfig property "enable_dr_programming_log" is off, all status of shift_dr registers will be removed when programming Jtag registers

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 79585 shift_ir 28(24____) 058905____
cycle 79619 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_453B) jtagConfig property "enable_dr_programming_log" is on, all shift_dr register status will be logged when programming
INFO_MBIST: Scanning out results from central MBIST chain for chiplet s0_0(SHX_S0)...
INFO: ramList_1_0 doesn't exist
INFO: ramList_1_1 doesn't exist
INFO: ramList_1_2 doesn't exist
INFO: ramList_1_3 doesn't exist
INFO: ramList_1_4 doesn't exist
INFO: ramList_1_5 doesn't exist

##################
INFO: executing SubTest INIT Sequence ...
(INFO:VEC_378) Cycle Info: wait_cycles (start@27241, end@27359) = 119 cycles. Accumulated 290 cycles.
(INFO:AFU_057) In label 'SUBTEST_INIT_END' dump signature 'V0_10342'
(INFO:VEC_378) Cycle Info: wait_cycles (start@27360, end@27360) = 1 cycles. Accumulated 291 cycles.
INFO: executing API: ::ATE::mbist::Short -prgmConfig $prgmConfig -testConfig $testConfig -chipletId 1
INFO: Reading Xml Files...
INFO_MBIST: MBIST Masking domains d={1 {}} r=1 n=1 c=1 j=0 j=1
INFO_MBIST: DomainMaskList before: {1 {}}
INFO_MBIST: DomainMaskList after: {1 {}}
INFO_MBIST: DEBUG_WAIT_CYCLE: --------------------------------------------------
INFO_MBIST: DEBUG_WAIT_CYCLE: regionName SHXS0XAL: masked domain List inside wait_cycle_calculation:
INFO_MBIST: DEBUG_WAIT_CYCLE: --------------------------------------------------
INFO_MBIST: DEBUG_WAIT_CYCLE: Total Me_Cnt (finalMe:5- initMe:4) : 2
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL_write cycles : 5376
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL_read cycles : 2688
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_DP_MUL cycles : 8064
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_SP_MUL cycles : 296
INFO_MBIST: DEBUG_WAIT_CYCLE: Total_PDP_MUL cycles : 43048

INFO_MBIST: Calculated waitcycle for region_inst : shxs0lnkm is 46146

INFO_MBIST: INFO used in wait_cycle calculation : design_type :rtl

INFO_MBIST: INFO used in wait_cycle calculation : clock_mode :jtag_bypass

INFO_MBIST: INFO used in wait_cycle calculation : chiplet_inst : SHX_S0

INFO_MBIST: INFO used in wait_cycle calculation : jtag_freq : 200

INFO_MBIST: INFO used in wait_cycle calculation : subtest : Short

INFO_MBIST: waitCycles required to complete all chiplets :50242

INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 27361. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/TOP_FS, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 27361 shift_ir 28(24____) 052405____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/TOP_FS
cycle 27395 shift_dr 46(42____) 00000000000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 27450. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/JTAG_FUSE_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 27450 shift_ir 28(24____) 052f05____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/JTAG_FUSE_CTRL
cycle 27484 shift_dr 143(139____) 3c000000000000000000000000000000000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 27632. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/CHIPLET_LOGIC, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 27632 shift_ir 28(24____) 052605____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/CHIPLET_LOGIC
cycle 27666 shift_dr 500(496____) 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28175. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/I1500_CHAIN_CTRL, s0_0/SHX_S0_1500_wrapper/WS_BYPASS, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28175 shift_ir 28(24____) 890505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/testmaster/I1500_CHAIN_CTRL
cycle 28209 shift_dr 9(5____) 10____
expected XXXXX____
(INFO:VEC_301) Cycle 28218 ChainIndex=6 shift register "s0_0/testmaster/testmaster_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28220 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/testmaster/testmaster_cli_inst" : BROADCAST = ON.
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28223. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/WS_BYPASS, t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
cycle 28223 shift_ir 28(24____) 050589____
(INFO:VEC_232) Shifting data to jtag registers: t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
cycle 28257 shift_dr 9(5____) 04____
expected XXXXX____
(INFO:VEC_301) Cycle 28264 ChainIndex=4 shift register "t0_0/SHX_T0_1500_wrapper/shxt0pads0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28266 ChainIndex=6 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "t0_0/SHX_T0_1500_wrapper/shxt0pads0_cli_inst" : BROADCAST = ON.
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28271. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28271 shift_ir 28(24____) 058905____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL

expected XXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 28314 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28316 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 28317 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28319 ChainIndex=11 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 28320 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28322 ChainIndex=14 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 28323 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28325 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 28326 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28328 ChainIndex=20 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 28329 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28331 ChainIndex=23 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON.
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28339. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_CTL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28339 shift_ir 28(24____) 051505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_CTL
cycle 28373 shift_dr 19(15____) 0000____
expected XXXXXXXXXXXXXXX____
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28401. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/I1500_CHAIN_CTRL, s0_0/SHX_S0_1500_wrapper/WS_BYPASS, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28401 shift_ir 28(24____) 890505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/testmaster/I1500_CHAIN_CTRL
cycle 28435 shift_dr 9(5____
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_CTL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28339 shift_ir 28(24____) 051505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_CTL
cycle 28373 shift_dr 19(15____) 0000____
expected XXXXXXXXXXXXXXX____
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28401. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/I1500_CHAIN_CTRL, s0_0/SHX_S0_1500_wrapper/WS_BYPASS, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28401 shift_ir 28(24____) 890505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/testmaster/I1500_CHAIN_CTRL
cycle 28435 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_301) Cycle 28444 ChainIndex=6 shift register "s0_0/testmaster/testmaster_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28446 ChainIndex=8 Programming value 1'h1 --> 1'h0 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/testmaster/testmaster_cli_inst" : BROADCAST = OFF.
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28449. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/WS_BYPASS, t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
cycle 28449 shift_ir 28(24____) 050589____
(INFO:VEC_232) Shifting data to jtag registers: t0_0/SHX_T0_1500_wrapper/I1500_CHAIN_CTRL
cycle 28483 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_301) Cycle 28490 ChainIndex=4 shift register "t0_0/SHX_T0_1500_wrapper/shxt0pads0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 28492 ChainIndex=6 Programming value 1'h1 --> 1'h0 for field="broadcast_write"
(INFO:VEC_365) Client "t0_0/SHX_T0_1500_wrapper/shxt0pads0_cli_inst" : BROADCAST = OFF.
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 28497. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 28497 shift_ir 28(24____) 058905____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL

expected XXXXXXXXXXXXXXXXXXXXX____

(INFO:VEC_301) Cycle 28540 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28542 ChainIndex=8 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_301) Cycle 28543 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28545 ChainIndex=11 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_301) Cycle 28546 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28548 ChainIndex=14 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_301) Cycle 28549 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28551 ChainIndex=17 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_301) Cycle 28552 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28554 ChainIndex=20 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_301) Cycle 28555 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28557 ChainIndex=23 Programming value 1'h1 --> 1'h0 for field="broadcast_write"

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = OFF.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = OFF.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = OFF.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = OFF.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = OFF.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = OFF.

INFO_MBIST: asserting mbist_ramaccess_rst_ 1

INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on

INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 28565 shift_ir 28(24____) 058905____

(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL

cycle 28599 shift_dr 25(21____) 092490____

expected XXXXXXXXXXXXXXXXXXXXX____

INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 28565 shift_ir 28(24____) 058905____

(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL

cycle 28599 shift_dr 25(21____) 092490____

expected XXXXXXXXXXXXXXXXXXXXX____

(INFO:VEC_301) Cycle 28608 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28610 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_301) Cycle 28611 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28613 ChainIndex=11 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_301) Cycle 28614 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28616 ChainIndex=14 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_301) Cycle 28617 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28619 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_301) Cycle 28620 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28622 ChainIndex=20 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_301) Cycle 28623 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"

(INFO:VEC_300A) Cycle 28625 ChainIndex=23 Programming value 1'h0 --> 1'h1 for field="broadcast_write"

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.

(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON.

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 28629 shift_ir 28(24____) 051a05____

(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL

cycle 28663 shift_dr 32(28____) 0000000____

expected XXXXXXXXXXXXXXXXXXXXXXXXXXXX____

(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared

(INFO:VEC_379) Cycle Info: move_to_state (start@28700, end@28749) = 50 cycles. Accumulated 50 cycles (end state = RUN_TEST_IDLE, the number of TCK cycles stay on end state = 50).

INFO_MBIST: desserting mbist_ramaccess_rst_

INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on

INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 28750 shift_ir 28(24____) 051a05____

(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL

cycle 28784 shift_dr 32(28____) 0002000____

expected XXXXXXXXXXXXXXXXXXXXXXXXXXXX____

(INFO:VEC_301) Cycle 28793 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/RAM_ACCESS_CTRL"

(INFO:VEC_300A) Cycle 28804 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="u0/mbist_ramaccess_rst_"

(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared

(INFO:VEC_379) Cycle Info: move_to_state (start@28821, end@28870) = 50 cycles. Accumulated 100 cycles (end state = RUN_TEST_IDLE, the number of TCK cycles stay on end state = 50).

INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on

INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/MBIST_TOP, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 28871 shift_ir 28(24____) 051605____

(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP

cycle 28905 shift_dr 197(193____) 0000000000000000000000000000000000000000000000008____

expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____

(INFO:VEC_301) Cycle 28914 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/MBIST_TOP"

(INFO:VEC_300A) Cycle 28915 ChainIndex=7 Programming value 1'h0 --> 1'h1 for field="u0/start_bits"

(INFO:VEC_300A) Cycle 28938 ChainIndex=30 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"

(INFO:VEC_300A) Cycle 28939 ChainIndex=31 Programming value 30'h3fffffff --> 30'h00000000 for field="u0/bist_mask_bits"

(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared

INFO: ramList_1_0 doesn't exist

INFO: ramList_1_1 doesn't exist

INFO: ramList_1_2 doesn't exist

INFO: ramList_1_3 doesn't exist

INFO: ramList_1_4 doesn't exist

INFO: ramList_1_5 doesn't exist

INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on

INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=

INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5

(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/MBIST_TOP, t0_0/SHX_T0_1500_wrapper/WS_BYPASS

cycle 29107 shift_ir 28(24____) 051605____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
cycle 29141 shift_dr 197(193____) 0000000000000000000000000000000000000000004814118____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 29150 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 29152 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 29154 ChainIndex=10 Programming value 8'h00 --> 8'h04 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 29162 ChainIndex=18 Programming value 8'h00 --> 8'h05 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 29171 ChainIndex=27 Programming value 1'h0 --> 1'h1 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 29174 ChainIndex=30 Programming value 1'h0 --> 1'h1 for field="u0/bist_mask_sel_bits"
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: Waiting 50242 Cycles for MBIST test to complete...
(INFO:VEC_378) Cycle Info: wait_cycles (start@29343, end@79584) = 50242 cycles. Accumulated 50533 cycles.
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is serial
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass region_without_mbist =
INFO_MBIST: DEBUG_BROADCAST: regions in bypass
INFO_MBIST: DEBUG_BROADCAST: regions in serial 0 1 2 3 4 5
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = OFF.
(WARN:VEC_453A) jtagConfig property "enable_dr_programming_log" is off, all status of shift_dr registers will be removed when programming Jtag registers
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 79585 shift_ir 28(24____) 058905____
cycle 79619 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_453B) jtagConfig property "enable_dr_programming_log" is on, all shift_dr register status will be logged when programming
INFO_MBIST: Scanning out results from central MBIST chain for chiplet s0_0(SHX_S0)...
INFO: ramList_1_0 doesn't exist
INFO: ramList_1_1 doesn't exist
INFO: ramList_1_2 doesn't exist
INFO: ramList_1_3 doesn't exist
INFO: ramList_1_4 doesn't exist
INFO: ramList_1_5 doesn't exist
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 79633. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/MBIST_TOP, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 79633 shift_ir 28(24____) 051605____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
cycle 79667 shift_dr 1147(1143____) 00000000000000000000000000000000000000000000000a0000000000000000000000000000000000000000000000280000000000000000000000000000000000000000000000a0000000000000000000000000000000000000000000000280000000000000000000000000000000000000000000000a000000000000000000000000000000000000000000000028____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXX00000101111XXX____
(INFO:VEC_301) Cycle 79676 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 79678 ChainIndex=8 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 79679 ChainIndex=9 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 79680 ChainIndex=10 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 79688 ChainIndex=18 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 79697 ChainIndex=27 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 79700 ChainIndex=30 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
(INFO:VEC_301) Cycle 79866 ChainIndex=196 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 79868 ChainIndex=198 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 79869 ChainIndex=199 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 79870 ChainIndex=200 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 79878 ChainIndex=208 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 79887 ChainIndex=217 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 79890 ChainIndex=220 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
(INFO:VEC_301) Cycle 80056 ChainIndex=386 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 80058 ChainIndex=388 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 80059 ChainIndex=389 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 80060 ChainIndex=390 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 80068 ChainIndex=398 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 80077 ChainIndex=407 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 80080 ChainIndex=410 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
(INFO:VEC_301) Cycle 80246 ChainIndex=576 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 80248 ChainIndex=578 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 80249 ChainIndex=579 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 80250 ChainIndex=580 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 80258 ChainIndex=588 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 80267 ChainIndex=597 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 80270 ChainIndex=600 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
(INFO:VEC_301) Cycle 80436 ChainIndex=766 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 80438 ChainIndex=768 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 80439 ChainIndex=769 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 80440 ChainIndex=770 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 80448 ChainIndex=778 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 80457 ChainIndex=787 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 80460 ChainIndex=790 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
(INFO:VEC_301) Cycle 80626 ChainIndex=956 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 80628 ChainIndex=958 Programming value 1'h1 --> 1'h0 for field="u0/run_base_bits"
(INFO:VEC_300A) Cycle 80629 ChainIndex=959 Programming value 1'h0 --> 1'h1 for field="u0/done_bits"
(INFO:VEC_300A) Cycle 80630 ChainIndex=960 Programming value 8'h04 --> 8'h00 for field="u0/elem_count_bits"
(INFO:VEC_300A) Cycle 80638 ChainIndex=968 Programming value 8'h05 --> 8'h00 for field="u0/final_me_bits"
(INFO:VEC_300A) Cycle 80647 ChainIndex=977 Programming value 1'h1 --> 1'h0 for field="u0/enable_bist_bits"
(INFO:VEC_300A) Cycle 80650 ChainIndex=980 Programming value 1'h1 --> 1'h0 for field="u0/bist_mask_sel_bits"
INFO_MBIST: Select chain daisy_mbist_status_chain for clusterInst SHX_S0_1500_wrapper
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 80823 shift_ir 28(24____) 058905____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
cycle 80857 shift_dr 25(21____) 092490____
expected XXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 80866 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80868 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 80869 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80871 ChainIndex=11 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 80872 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80874 ChainIndex=14 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 80875 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80877 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 80878 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80880 ChainIndex=20 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 80881 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 80883 ChainIndex=23 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON.
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 80887 shift_ir 28(24____) 051a05____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
cycle 80921 shift_dr 32(28____) 4063fe0____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 80930 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/RAM_ACCESS_CTRL"
(INFO:VEC_300A) Cycle 80931 ChainIndex=7 Programming value 10'h000 --> 10'h3fc for field="u0/chain_sel"
(INFO:VEC_300A) Cycle 80945 ChainIndex=21 Programming value 1'h0 --> 1'h1 for field="u0/clk_switch_en"
(INFO:VEC_300A) Cycle 80946 ChainIndex=22 Programming value 1'h0 --> 1'h1 for field="u0/shift_only"
(INFO:VEC_300A) Cycle 80954 ChainIndex=30 Programming value 1'h0 --> 1'h1 for field="u0/debug_on"
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is serial
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass region_without_mbist =
INFO_MBIST: DEBUG_BROADCAST: regions in bypass
INFO_MBIST: DEBUG_BROADCAST: regions in serial 0 1 2 3 4 5
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = OFF.
(WARN:VEC_453A) jtagConfig property "enable_dr_programming_log" is off, all status of shift_dr registers will be removed when programming Jtag registers
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 80958 shift_ir 28(24____) 058905____
cycle 80992 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_453B) jtagConfig property "enable_dr_programming_log" is on, all shift_dr register status will be logged when programming
INFO_MBIST: Scanning out local mbist status chain for SHX_S0_1500_wrapper
INFO: ramList_1_0 doesn't exist
INFO: ramList_1_1 doesn't exist
INFO: ramList_1_2 doesn't exist
INFO: ramList_1_3 doesn't exist
INFO: ramList_1_4 doesn't exist
INFO: ramList_1_5 doesn't exist
(INFO:VEC_263) PrgmConfig begins to shift a chain at cycle 81006. Chain data is shown in following messages:
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_DATA_mbist_sts, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 81006 shift_ir 28(24____) 050d05____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_DATA_mbist_sts
cycle 81040 shift_dr 7653(7649____) 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000X00000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000X000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000X000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000X00000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000X00000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000X00000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000X000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000000X0000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000000X0000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000000X0000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00000X1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000000X0000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000X00000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000X00000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX000000000000000X000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000X00000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000010XXXX____
INFO_MBIST: Deasserting debug mode for configIndex 1
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 88702 shift_ir 28(24____) 058905____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
cycle 88736 shift_dr 25(21____) 092490____
expected XXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 88745 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88747 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88748 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88750 ChainIndex=11 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88751 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88753 ChainIndex=14 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88754 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88756 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88757 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88759 ChainIndex=20 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88760 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88762 ChainIndex=23 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON.
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 88766 shift_ir 28(24____) 051a05____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_ACCESS_CTRL
cycle 88800 shift_dr 32(28____) 0002000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 88809 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/RAM_ACCESS_CTRL", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/RAM_ACCESS_CTRL"
(INFO:VEC_300A) Cycle 88810 ChainIndex=7 Programming value 10'h3fc --> 10'h000 for field="u0/chain_sel"
(INFO:VEC_300A) Cycle 88824 ChainIndex=21 Programming value 1'h1 --> 1'h0 for field="u0/clk_switch_en"
(INFO:VEC_300A) Cycle 88825 ChainIndex=22 Programming value 1'h1 --> 1'h0 for field="u0/shift_only"
(INFO:VEC_300A) Cycle 88833 ChainIndex=30 Programming value 1'h1 --> 1'h0 for field="u0/debug_on"
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is serial
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass region_without_mbist =
INFO_MBIST: DEBUG_BROADCAST: regions in bypass
INFO_MBIST: DEBUG_BROADCAST: regions in serial 0 1 2 3 4 5
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = OFF.
(WARN:VEC_453A) jtagConfig property "enable_dr_programming_log" is off, all status of shift_dr registers will be removed when programming Jtag registers
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 88837 shift_ir 28(24____) 058905____
cycle 88871 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_453B) jtagConfig property "enable_dr_programming_log" is on, all shift_dr register status will be logged when programming
INFO_MBIST: clearing out registers
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 88885 shift_ir 28(24____) 058905____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL
cycle 88919 shift_dr 25(21____) 092490____
expected XXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 88928 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88930 ChainIndex=8 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88931 ChainIndex=9 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88933 ChainIndex=11 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88934 ChainIndex=12 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88936 ChainIndex=14 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88937 ChainIndex=15 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88939 ChainIndex=17 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88940 ChainIndex=18 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88942 ChainIndex=20 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_301) Cycle 88943 ChainIndex=21 shift register "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/I1500_CHAIN_CTRL"
(INFO:VEC_300A) Cycle 88945 ChainIndex=23 Programming value 1'h0 --> 1'h1 for field="broadcast_write"
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = ON.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = ON.
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/MBIST_TOP, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 88949 shift_ir 28(24____) 051605____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/MBIST_TOP
cycle 88983 shift_dr 197(193____) 0000000000000000000000000000000000000000000000000____
expected XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 88992 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/MBIST_TOP", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/MBIST_TOP"
(INFO:VEC_300A) Cycle 88993 ChainIndex=7 Programming value 1'h1 --> 1'h0 for field="u0/start_bits"
(INFO:VEC_300A) Cycle 88995 ChainIndex=9 Programming value 1'h1 --> 1'h0 for field="u0/done_bits"
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is broadcast_on
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in bypass c=1 r=
INFO_MBIST: DEBUG_BROADCAST: regions in broadcast c=1 r= 0 1 2 3 4 5
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/RAM_CTL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 89185 shift_ir 28(24____) 051505____
(INFO:VEC_232) Shifting data to jtag registers: s0_0/SHX_S0_1500_wrapper/RAM_CTL
cycle 89219 shift_dr 19(15____) 0100____
expected XXXXXXXXXXXXXXX____
(INFO:VEC_301) Cycle 89228 ChainIndex=6 shift register "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst/RAM_CTL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst/RAM_CTL", "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst/RAM_CTL", "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst/RAM_CTL", "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst/RAM_CTL", "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst/RAM_CTL"
(INFO:VEC_300A) Cycle 89234 ChainIndex=12 Programming value 1'h0 --> 1'h1 for field="u0/write_inh"
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: DEBUG_BROADCAST: MBIST mode is serial
INFO_MBIST: DEBUG_BROADCAST: region passed to be on bypass region_without_mbist =
INFO_MBIST: DEBUG_BROADCAST: regions in bypass
INFO_MBIST: DEBUG_BROADCAST: regions in serial 0 1 2 3 4 5
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnkm_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk0_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0lnk1_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xpl_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xtq_cli_inst" : BROADCAST = OFF.
(INFO:VEC_365) Client "s0_0/SHX_S0_1500_wrapper/shxs0xal_cli_inst" : BROADCAST = OFF.
(WARN:VEC_453A) jtagConfig property "enable_dr_programming_log" is off, all status of shift_dr registers will be removed when programming Jtag registers
(INFO:VEC_546) shift_ir: register list = s0_0/testmaster/WS_BYPASS, s0_0/SHX_S0_1500_wrapper/I1500_CHAIN_CTRL, t0_0/SHX_T0_1500_wrapper/WS_BYPASS
cycle 89243 shift_ir 28(24____) 058905____
cycle 89277 shift_dr 9(5____) 00____
expected XXXXX____
(INFO:VEC_453B) jtagConfig property "enable_dr_programming_log" is on, all shift_dr register status will be logged when programming
(INFO:VEC_464) PrgmConfig::clear_program_value called. All program value set by PrgmConfig::set_program_value is cleared
INFO_MBIST: Moving to RTI state
JTAG init to state: RTI
(INFO:VEC_379) Cycle Info: move_to_state (start@89291, end@89300) = 10 cycles. Accumulated 110 cycles (end state = RUN_TEST_IDLE, the number of TCK cycles stay on end state = 10).
(INFO:ATE_105) procedure '::ATE::mbist::Short' execute time is: 38 mins 48 secs

INFO: executing Global EOT Sequence ...
(INFO:VEC_378) Cycle Info: wait_cycles (start@89301, end@89399) = 99 cycles. Accumulated 50632 cycles.
(INFO:AFU_057) In label 'EOT_BEGIN' dump signature 'V0_40996'
(INFO:VEC_378) Cycle Info: wait_cycles (start@89400, end@89400) = 1 cycles. Accumulated 50633 cycles.
(INFO:ATE_109) 05/04/2020 10:59:58 starting global eot sequence 'BreakPoint Start_UPHY_Power_Off' @cycle 89401
(INFO:VEC_378) Cycle Info: wait_cycles (start@89401, end@89519) = 119 cycles. Accumulated 50752 cycles.
(INFO:AFU_057) In label 'Start_UPHY_Power_Off' dump signature 'V0_34450'
(INFO:VEC_378) Cycle Info: wait_cycles (start@89520, end@89520) = 1 cycles. Accumulated 50753 cycles.
(INFO:ATE_109) 05/04/2020 11:00:03 starting global eot sequence 'UPHY_Power_Off' @cycle 89521
05/04/2020 11:00:03==============@cycle 89521 ENTER procedure: ::UPHY_Power_Off==============
test_name is: mbist.mbist
subtest_name is: Short
design_type is: rtl
design_scope is: FULLCHIP
clock_mode is : jtag_bypass
sub_clock_mode is :
init modes: extest 0 testclk_trigger 0 tam 0 xtr 0 intest 0 serdesclk_trigger 0 fabric_pex 0 stuckat 0 ftm 0
sub_modes is:
ATE_config is:
UPHY PowerDown Sequence Enabled
05/04/2020 11:00:03==============@cycle 89521 LEAVE procedure: ::UPHY_Power_Off==============
(INFO:ATE_105) procedure '::UPHY_Power_Off' execute time is: 1 secs
(INFO:ATE_109) 05/04/2020 11:00:03 starting global eot sequence 'BreakPoint End_UPHY_Power_Off' @cycle 89521
(INFO:VEC_378) Cycle Info: wait_cycles (start@89521, end@89639) = 119 cycles. Accumulated 50872 cycles.
(INFO:AFU_057) In label 'End_UPHY_Power_Off' dump signature 'V0_35614'
(INFO:VEC_378) Cycle Info: wait_cycles (start@89640, end@89640) = 1 cycles. Accumulated 50873 cycles.
(INFO:VEC_378) Cycle Info: wait_cycles (start@89641, end@89759) = 119 cycles. Accumulated 50992 cycles.
(INFO:AFU_057) In label 'GLOBAL_EOT_END' dump signature 'V0_57754'
(INFO:VEC_378) Cycle Info: wait_cycles (start@89760, end@89760) = 1 cycles. Accumulated 50993 cycles.

INFO: executing Test EOT Sequence ...
(INFO:VEC_378) Cycle Info: wait_cycles (start@89761, end@89879) = 119 cycles. Accumulated 51112 cycles.
(INFO:AFU_057) In label 'TEST_EOT_END' dump signature 'V0_1325'
(INFO:VEC_378) Cycle Info: wait_cycles (start@89880, end@89880) = 1 cycles. Accumulated 51113 cycles.

INFO: executing SubTest EOT Sequence ...
(INFO:VEC_378) Cycle Info: wait_cycles (start@89881, end@89999) = 119 cycles. Accumulated 51232 cycles.
(INFO:AFU_057) In label 'SUBTEST_EOT_END' dump signature 'V0_55232'
(INFO:VEC_378) Cycle Info: wait_cycles (start@90000, end@90000) = 1 cycles. Accumulated 51233 cycles.
(INFO:VEC_313) TN->PLI: force tb.TB_sim_run 0 0 0
(INFO:VEC_378) Cycle Info: wait_cycles (start@90001, end@90001) = 1 cycles. Accumulated 51234 cycles.
(INFO:VEC_378) Cycle Info: wait_cycles (start@90002, end@90119) = 118 cycles. Accumulated 51352 cycles.
(INFO:AFU_057) In label 'END_OF_TEST' dump signature 'V0_7439'
(INFO:VEC_378) Cycle Info: wait_cycles (start@90120, end@90120) = 1 cycles. Accumulated 51353 cycles.
(INFO:AFU_061) Summary Disable Event Num: 2
(INFO:AFU_061) Summary Total Event Num: 136
normalCycleCount: 90121
###################################
# dft programming modes summary #
###################################
dft programming mode:
N/A

dft programming common modes:
s0_0: N/A
t0_0: N/A

short mbis

Display API 07:07 No comments

proc socf_base_mbist_interface { args_ref } {
upvar $args_ref args
set orig_args $args
global domainsXml

set options {
{svop.arg 00 "-svop"}
{prgmConfig.arg "" "-prgmConfig object" "NO_CUSTOMIZE"}
{testConfig.arg "" "<test config object>" "NO_CUSTOMIZE"}
{domainMaskList.arg "[list]" "-list of domains to be masked. Usage : -domainMaskList '{ {<1st cluster_id> {{<1st region_id> {<list of masked domain id>}}... {<Nth region_id> {<list of masked domain id>}}} }... {<Nth cluster_id> {{<1st region_id of Nth cluster> {<list of masked domain id>}}... {<Nth region_id of Nth cluster> {<list of masked domain id>}}} } }'"}
{domainUnMaskList.arg "" "-list of domains to be masked. Usage : -domainUnMaskList '{ {<1st cluster_id> {{<1st region_id> {<list of masked domain id>}}... {<Nth region_id> {<list of masked domain id>}}} }... {<Nth cluster_id> {{<1st region_id of Nth cluster> {<list of masked domain id>}}... {<Nth region_id of Nth cluster> {<list of masked domain id>}}} } }'"}
{initMe.arg.secret "" "-initial march element" "NO_CUSTOMIZE"}
{finalMe.arg.secret "" "-final march element" "NO_CUSTOMIZE"}
{dumpLocal.arg "1" "-option to dump local chains. 1 to enable dumping."}
{dumpMemoryHostAccess.arg "0" "-option to dump local Memory/Host Access chains. 1 to enable dumping."}
{regionMaskList.arg "[list]" "-list of regions to be masked"}
{region_inst.arg "ALL_REGION" "-targeted region"}
{regionId.arg "-1" "-targeted region"}
{chipletId.arg "-1" "-targeted chiplet"}
{waitCycles.arg 500 "-default waitCycles between writes and reads"}
{bist_on.arg "0" "-keep mbist_en asserted at end of the end"}
{waitcycle_override.arg 0 ""}
{subtest.arg "" "Type of test"}
{err_inj_type.arg "" "ERR INJ Type"}
{pll_freq_list.arg "" "path of pll_freq_list"}
{dumpCentral.arg "1" "-option to dump local chains. 1 to enable dumping."}
{Ram_UnMask.arg "None" "specify type of ram to be Unmasked"}
{Ram_Mask.arg "None" "specify type of ram to be Masked"}
{wr_all_lane.arg "0" "For writing into all lanes one by one"}
{wr_one_lane.arg "-1" "For writing into only the selected lane"}
{ramSettings.arg "" "-ramSettings list. Usage -ramSettings {{<field_name1> value} {<field_name2> value} ...} "}
{Clk_UnMask.arg "None" "specify name of clock to be Unmasked"}
{Clk_Mask.arg "None" "specify name of clock to be Masked"}
{enable_crc_dump.arg "-1" "option to enable crc dump"}
{enable_crc_cmp.arg "-1" "option to enable crc compare"}
{flat_mode.arg "0" "option to switch between rtl(0) and flat(1) mode"}
{NoRst.arg "0" "-NoRst"}
{number_of_splits.arg "1" "Number of iterations in which we want to split the pattern"}
{clear_mbist_toggle.arg "0" "by default do mot toggle clear_mbist once at the beginning"}
{lpc_prog_on.arg "1" "by default lpc programming will be enabled in chip having lpc inseterd mbist"}
{staggered_mode.arg "1" "Start finishing status as soon as MBIST operation finshes on chiplets rather than waiting for other chiplet to get finished"}
{enable_wait_absolute.arg "0" "enable absolute wait time"}
{ctrl_chain_mode.arg "broadcast_mbist_ctrl_chain" "disable broadcast mode in for ctrl chain gv100 onward"}
{host_chain_mode.arg "mbist_hostaccess_chain" "shift local status chain indaisy mode gv100 onward"}
{status_chain_mode.arg "daisy_mbist_status_chain" "shift local control chain shift in in daisy mode gv100 onward"}
{jtag_broadcast_client.arg "1" "use jtag broadcast for clients wherever possible"}
{jtag_broadcast_cluster.arg "0" "use jtag broadcast for cluster wherever possible"}
{full_test_final_me_override.arg "0" "used for pickingup ull test FinalMe from full_test_finalme_override key"}
{ist_mode_mbist.arg "0" "-enable IST mode"}
{no_ist_seq_markers.arg "0" "-remove sequence markers in ist_mode"}
{last_seq_mbistwait.arg "0" "-mbist wait will be the last seq"}
{cfg_access_latency.arg "" "program access latency in Rams which have this feature"}
{cfg_rdata_pipeline.arg "" "program rd data pipeline"}
{toggle_rst.arg "0" "toggling mbist_ramacces_rst_ after getting mbist_en high"}
{dummy_mbist_en.arg "1" "set mbist_en high before setting enable_bist"}
{debug_mode_wr_inh.arg "0" "toggle debug_mode during debug_mode toggling"}
{pid_failed_yaml.arg "" "to be only used regression or vec mode for mbist_step mode"}
{use_read_ram.arg "0" "use read_ram instead of flush_ram in step_mode proc"}
{access_latency.arg "" ""}
{rdata_pipeline.arg "" ""}
{gui_mode.arg "0" "-enable scan debug gui mode"}
{rd_on.arg "0" "-switch to read and shiftout ram content"}
{repairable.arg "" "for two pass mbist_step_mode verification -one for repairable rams "}
{cluster_list.arg "" "-list of clusters to be run"}
{fs_group_list.arg "" "-fs region grouping for IST"}
{partial_mbist_central_comp.arg "0" "compare only mbist enable when ist_mbist_mode is set to 1"}
{set_wr_inh.arg "1" "set RAM_CTL wr_inh bit to 1"}
{prgm_ram_ctl.arg "1" "clear RAM_CTL in the begining"}
{rdpath_x_clear_seq.arg "0" "clear rams to avoid x propagation in gates"}
{skip_chkbd_rd.arg "0" "skip read chkbd step in the memory initialization"}
{gen_emulation_vec.arg "0" "generate vec mode for emulation- step1 -for error generating log step2-running step_mode"}
{expect_lfsr_0.arg "0" "will set expected value on lfsr to all 0"}
{mbist_assertion.arg "0" "enable mbist s3 assertion"}
{stagger_programming_cycle.arg "0" "stagger MBIST_TOP programming between clusters by this cycle number"}
{split_programming.arg "0" "split MBIST_TOP programming into 4 groups"}
{set_top_fs.arg "0" "set top_fs register bits to 1"}
{use_scan_debug_ctl.arg "1" "choose between scan_debug_ctl or CLK_PCCM_CTL for switching off clock in split programming mode"}
{clear_serial_shift.arg "0" "use serial clear shift of 1500_chain_ctrl"}
{marker_suffix.arg "" "additional suffix needed for IST"}
{ist_clk_freq.arg "" "provide ist_clk_freq in case of ist tests"}
{run_short_nc.arg "1" "run short with no compare"}
{enableFlag.arg "0" "add enable or diasbleflag for ramlist"}
{use_be_id.arg "1" "run short with no compare"}
{ramList.arg "" "ramList to be enabled disabled"}
{mask_all_rams.arg "0" "argument to shift local chainwith mask_all_rams"}
{FA_shift_out.arg "0" "shift in ram_access_chain "}
{stop_on_first_error.arg "0" "set stop on first error bit for FA"}
{ListArgs.arg "" "-option helper"}
}

array set params [::cmdline::getKnownOptions args $options ]
if { $params(ListArgs) != "" } {
upvar $params(ListArgs) fullopt
set options "$fullopt $options"
set fullopt $options
return
} else {
# parray params
# puts "INFO_MBIST: remain args: $args"
}

if { $params(ListArgs) == "" } {
set prgmConfig $params(prgmConfig)
set jtagConfig [$prgmConfig get_jtag_config]
set testConfig $params(testConfig)
set domainMaskList $params(domainMaskList)
set domainUnMaskList $params(domainUnMaskList)
set initMe $params(initMe)
set finalMe $params(finalMe)
set dumpLocal $params(dumpLocal)
set dumpMemoryHostAccess $params(dumpMemoryHostAccess)
set regionMaskList $params(regionMaskList)
set wait_time $params(waitCycles)
set bist_on $params(bist_on)
set svop $params(svop)
set subtest $params(subtest)
set set_wr_inh $params(set_wr_inh)
set prgm_ram_ctl $params(prgm_ram_ctl)
set rdpath_x_clear_seq $params(rdpath_x_clear_seq)
set skip_chkbd_rd $params(skip_chkbd_rd)
set err_inj_type $params(err_inj_type)
set pll_freq_list $params(pll_freq_list)
set waitcycle_override $params(waitcycle_override)
set jtagConfigList [$jtagConfig jtag_config_list]
set dumpCentral $params(dumpCentral)
set Ram_UnMask $params(Ram_UnMask)
set Ram_Mask $params(Ram_Mask)
set wr_all_lane $params(wr_all_lane)
set wr_one_lane $params(wr_one_lane)
set region_inst $params(region_inst)
set regionId $params(regionId)
set chipletId $params(chipletId)
set ram_settings_list $params(ramSettings)
set Clk_Mask $params(Clk_Mask)
set Clk_UnMask $params(Clk_UnMask)
set enable_crc_dump $params(enable_crc_dump)
set enable_crc_cmp $params(enable_crc_cmp)
set flat_mode $params(flat_mode)
set NoRst $params(NoRst)
set number_of_splits $params(number_of_splits)
set clear_mbist_toggle $params(clear_mbist_toggle)
set lpc_prog_on $params(lpc_prog_on)
set enable_wait_absolute $params(enable_wait_absolute)
set ctrl_chain_mode $params(ctrl_chain_mode)
set host_chain_mode $params(host_chain_mode)
set status_chain_mode $params(status_chain_mode)
set regionId $params(regionId)
set jtag_broadcast_client $params(jtag_broadcast_client)
set jtag_broadcast_cluster $params(jtag_broadcast_cluster)
set full_test_final_me_override $params(full_test_final_me_override)
set ist_mode_mbist $params(ist_mode_mbist)
set last_seq_mbistwait $params(last_seq_mbistwait)
set no_ist_seq_markers $params(no_ist_seq_markers)
set cfg_access_latency $params(cfg_access_latency)
set cfg_rdata_pipeline $params(cfg_rdata_pipeline)
set toggle_rst $params(toggle_rst)
set dummy_mbist_en $params(dummy_mbist_en)
et pid_failed_yaml $params(pid_failed_yaml)
set access_latency $params(access_latency)
set rdata_pipeline $params(rdata_pipeline)
set gui_mode $params(gui_mode)
set rd_on $params(rd_on)
set repairable $params(repairable)
set cluster_list $params(cluster_list)
set fs_group_list $params(fs_group_list)
set partial_mbist_central_comp $params(partial_mbist_central_comp)
set gen_emulation_vec $params(gen_emulation_vec)
set expect_lfsr_0 $params(expect_lfsr_0)
set mbist_assertion $params(mbist_assertion)
set stagger_programming_cycle $params(stagger_programming_cycle)
set set_top_fs $params(set_top_fs)
set split_programming $params(split_programming)
set use_scan_debug_ctl $params(use_scan_debug_ctl)
set clear_serial_shift $params(clear_serial_shift)
set marker_suffix $params(marker_suffix)
set ist_clk_freq $params(ist_clk_freq)
set run_short_nc $params(run_short_nc)
set ramList $params(ramList)
set use_be_id $params(use_be_id)
set enableFlag $params(enableFlag)
set mask_all_rams $params(mask_all_rams)
set FA_shift_out $params(FA_shift_out)
set stop_on_first_error $params(stop_on_first_error)

if {!$gui_mode} {
socf_read_xmlFiles $testConfig
}

$prgmConfig set_property single_controller_per_shift "force_enable"

if {$gen_emulation_vec} {
puts "INFO_MBIST: prograrming ATPG_CTL spare bit"
$prgmConfig set_program_value ".*/ATPG_CTL" ".*ATPG_CTL_spare_bit.*" -value 1'b1
$prgmConfig program
}
set starting_cycle [get_current_cycle $jtagConfig]

set regionConfig [config_map_value $domainsXml "region_list"]
if {[config_has_key $regionConfig "pseudo_clust_inst" ]} {
set temp [config_list [config_find $testConfig CURRENT_TEST/CURRENT_SUBTEST/TESTSCRIPT_DEFINED_ARGS/chiplet_name] ]
regsub {_cli$} $temp {} temp
set temp [string tolower $temp]
# append temp2 $temp "_cli_inst"
set region_inst $temp
}

if { [config_map_value [config_find $testConfig CURRENT_TEST] design_scope] == "FULLCHIP" } {
if { $chipletId != -1 } {
set chiplet_hier_inst [socf_get_chiplet_inst $jtagConfigList $chipletId]
set configIndex $chipletId
set chiplet_inst [[lindex $jtagConfigList $configIndex] controller_type]
regsub {_clstr$} $chiplet_inst {} chiplet_inst
if { ![chipletHasRams $domainsXml $chiplet_inst] } {puts "INFO_MBIST: chiplet $chiplet_inst doesn't have any rams, please provide chipletId which has rams" ; exit 1}
} else {
set chiplet_inst "FULLCHIP"
set configIndex [chipletInst_to_configIndex $jtagConfigList $chiplet_inst $domainsXml]
}
} else {
set chiplet_inst [config_map_value [config_find $testConfig CURRENT_TEST] design_scope]
set configIndex [chipletInst_to_configIndex $jtagConfigList $chiplet_inst $domainsXml]
}
###For step mode verif test
if {[regexp {mbist_step_mode} $subtest ]} {
set failedTagConfig [config_new_map]
set failed_tags [list]
set rams_to_be_run 1
if {$repairable} {
###Prepare ram_mask list for masking out non_reapiarable RAMS
set ramList [lindex [get_ram_mask_list_repairable_be $domainsXml ] 1]
set use_be_id 1
set enableFlag 1
if { [llength $ramList] == 0} {
set rams_to_be_run 0
}
} else {
###Prepare ram_mask list for masking out reapiarable RAMS
set ramList [lindex [get_ram_mask_list_repairable_be $domainsXml] 1]
set rams_to_be_run [lindex [get_ram_mask_list_repairable_be $domainsXml] 0]
set use_be_id 1
set enableFlag 0
}
puts "INFO_MBIST: DBG_STEP_MODE: ramList = $ramList enableFlag = $enableFlag rams_to_be_run = $rams_to_be_run"
}
set t [llength $domainUnMaskList]
if {[llength $domainUnMaskList] > 0 } {
set domainMaskList [get_domain_mask_list_frm_unmask $jtagConfigList $domainsXml $configIndex $domainUnMaskList]
puts "INFO_MBIST: DomainUnMaskList $domainUnMaskList"
puts "INFO_MBIST: DomainMaskList $domainMaskList"

}
if { $configIndex != -1 } { set staggered_mode 0 }
if { $waitcycle_override == 1 } { set staggered_mode 0 }
if { $regionId != -1 } { set region_inst [socf_get_region_inst $domainsXml $chiplet_inst $regionId] }

set design_type [config_map_value [config_find $testConfig CURRENT_TEST] design_type]
set clock_mode [config_map_value [config_find $testConfig CURRENT_TEST] clock_mode]

if {$gen_emulation_vec == 0} {

if { $err_inj_type == "all" } {
if {$run_short_nc == 1} {
set marchElemList "100000000100010000011 100000001000010000011"
puts "INFO_MBIST: running Short test with no compare "
if {($enable_crc_cmp == -1) && ($clock_mode eq "pll") } {
set enable_crc_cmp 1
}
if {$clock_mode eq "jtag_bypass"} {
if {[$prgmConfig jtag_output_type] == "VerilogXface"} {
if {$enable_crc_dump == -1} {
set enable_crc_dump 1
}
} else {
if {$enable_crc_cmp == -1} {
set enable_crc_cmp 1
}
}
}

socf_prog_bist $prgmConfig $jtagConfigList $configIndex $domainsXml {} $wait_time $marchElemList -chiplet_inst $chiplet_inst -regionMaskList $regionMaskList -subtest "ProgBist" -domainMaskList $domainMaskList -bist_on 1 -diag_en 3 -oneShift 1 -design_type $design_type -clock_mode $clock_mode -waitcycle_override $waitcycle_override -pll_freq_list $pll_freq_list -testConfig $testConfig -region_inst $region_inst -svop $svop -err_inj_type $err_inj_type -lpc_prog_on $lpc_prog_on -ctrl_chain_mode $ctrl_chain_mode -host_chain_mode $host_chain_mode -status_chain_mode $status_chain_mode -debug_mode_wr_inh $debug_mode_wr_inh -jtag_broadcast_client $jtag_broadcast_client -jtag_broadcast_cluster $jtag_broadcast_cluster -dummy_mbist_en $dummy_mbist_en -toggle_rst $toggle_rst -ist_mode_mbist $ist_mode_mbist -no_ist_seq_markers $no_ist_seq_markers -last_seq_mbistwait $last_seq_mbistwait -cfg_access_latency $cfg_access_latency -cfg_rdata_pipeline $cfg_rdata_pipeline -cluster_list $cluster_list -hi_addr "" -low_addr "" -hi_me "" -low_me "" -loop_en 0 -ramList $ramList -use_be_id $use_be_id -enable_crc_dump $enable_crc_dump -enable_crc_cmp $enable_crc_cmp -set_wr_inh 0 -mask_all_rams $mask_all_rams -marker_suffix Prog_nc
set NoRst 1
set clear_mbist_toggle 1

}

set err_inj_type_list [list firstAddr_firstCol secondAddr_lastCol firstSecondAddr_firstLastCol]
set set_wr_inh_final 0
foreach err_inj_type $err_inj_type_list {
if {$err_inj_type eq [lindex $err_inj_type_list [expr [llength $err_inj_type_list] -1]]} {
set set_wr_inh_final $set_wr_inh
}
socf_mbist_test $prgmConfig $jtagConfigList $configIndex $domainsXml -domainMaskList $domainMaskList -waitCycles $wait_time -initMe $initMe -finalMe $finalMe -oneShift 1 -chiplet_inst $chiplet_inst -dumpLocal $dumpLocal -regionMaskList $regionMaskList -bist_on 1 -design_type $design_type -clock_mode $clock_mode -waitcycle_override $waitcycle_override -subtest $subtest -err_inj_type $err_inj_type -pll_freq_list $pll_freq_list -testConfig $testConfig -dumpCentral $dumpCentral -wr_all_lane $wr_all_lane -wr_one_lane $wr_one_lane -region_inst $region_inst -svop $svop -ram_settings $ram_settings_list -dumpMemoryHostAccess $dumpMemoryHostAccess -Ram_Mask $Ram_Mask -Ram_UnMask $Ram_UnMask -Clk_Mask $Clk_Mask -Clk_UnMask $Clk_UnMask -NoRst $NoRst -enable_crc_dump $enable_crc_dump -enable_crc_cmp $enable_crc_cmp -flat_mode $flat_mode -clear_mbist_toggle $clear_mbist_toggle -staggered_mode $staggered_mode -lpc_prog_on $lpc_prog_on -enable_wait_absolute $enable_wait_absolute -ctrl_chain_mode $ctrl_chain_mode -host_chain_mode $host_chain_mode -status_chain_mode $status_chain_mode -debug_mode_wr_inh $debug_mode_wr_inh -jtag_broadcast_client $jtag_broadcast_client -jtag_broadcast_cluster $jtag_broadcast_cluster -dummy_mbist_en $dummy_mbist_en -toggle_rst $toggle_rst -gui_mode $gui_mode -ist_mode_mbist $ist_mode_mbist -no_ist_seq_markers $no_ist_seq_markers -last_seq_mbistwait $last_seq_mbistwait -cfg_access_latency $cfg_access_latency -cfg_rdata_pipeline $cfg_rdata_pipeline -cluster_list $cluster_list -fs_group_list $fs_group_list -jtag_broadcast_cluster $jtag_broadcast_cluster -partial_mbist_central_comp $partial_mbist_central_comp -full_test_final_me_override $full_test_final_me_override -set_wr_inh $set_wr_inh_final -prgm_ram_ctl $prgm_ram_ctl -rdpath_x_clear_seq $rdpath_x_clear_seq -expect_lfsr_0 $expect_lfsr_0 -skip_chkbd_rd $skip_chkbd_rd -stagger_programming_cycle $stagger_programming_cycle -split_programming $split_programming -set_top_fs $set_top_fs -clear_serial_shift $clear_serial_shift -ist_clk_freq $ist_clk_freq -marker_suffix $err_inj_type
set NoRst 1
set clear_mbist_toggle 1
}
} else {
set domainMaskList_backup $domainMaskList
set set_wr_inh_final 0
for {set run_number 1} {$run_number <= $number_of_splits } {incr run_number } {
if {$run_number == $number_of_splits} {
set set_wr_inh_final $set_wr_inh
}
if {![config_has_key $regionConfig "pseudo_clust_inst" ]} {
set domainMaskList $domainMaskList_backup
set domainMaskList [getLPdomainMaskList $jtagConfigList $configIndex $domainsXml $domainMaskList $run_number $number_of_splits $configIndex]
puts "INFO_MBIST: MBIST Masking domains d=$domainMaskList r=$run_number n=$number_of_splits c=$configIndex j=$jtag_broadcast_cluster j=$jtag_broadcast_client"
if {[llength $domainMaskList] && ($number_of_splits > 1)} {
clock_off_programming $prgmConfig $jtagConfigList $configIndex $domainsXml $domainMaskList -use_scan_debug_ctl $use_scan_debug_ctl
}
}

socf_mbist_test $prgmConfig $jtagConfigList $configIndex $domainsXml -domainMaskList $domainMaskList -waitCycles $wait_time -initMe $initMe -finalMe $finalMe -oneShift 1 -chiplet_inst $chiplet_inst -dumpLocal $dumpLocal -regionMaskList $regionMaskList -bist_on $bist_on -design_type $design_type -clock_mode $clock_mode -waitcycle_override $waitcycle_override -subtest $subtest -err_inj_type $err_inj_type -pll_freq_list $pll_freq_list -testConfig $testConfig -dumpCentral $dumpCentral -wr_all_lane $wr_all_lane -wr_one_lane $wr_one_lane -region_inst $region_inst -svop $svop -ram_settings $ram_settings_list -dumpMemoryHostAccess $dumpMemoryHostAccess -Ram_Mask $Ram_Mask -Ram_UnMask $Ram_UnMask -Clk_Mask $Clk_Mask -Clk_UnMask $Clk_UnMask -NoRst $NoRst -enable_crc_dump $enable_crc_dump -enable_crc_cmp $enable_crc_cmp -flat_mode $flat_mode -clear_mbist_toggle $clear_mbist_toggle -staggered_mode $staggered_mode -lpc_prog_on $lpc_prog_on -enable_wait_absolute $enable_wait_absolute -ctrl_chain_mode $ctrl_chain_mode -host_chain_mode $host_chain_mode -status_chain_mode $status_chain_mode -debug_mode_wr_inh $debug_mode_wr_inh -access_latency $access_latency -rdata_pipeline $rdata_pipeline -toggle_rst $toggle_rst -gui_mode $gui_mode -ramList $ramList -use_be_id $use_be_id -enableFlag $enableFlag -cluster_list $cluster_list -fs_group_list $fs_group_list -jtag_broadcast_client $jtag_broadcast_client -ist_mode_mbist $ist_mode_mbist -no_ist_seq_markers $no_ist_seq_markers -last_seq_mbistwait $last_seq_mbistwait -cfg_access_latency $cfg_access_latency -cfg_rdata_pipeline $cfg_rdata_pipeline -jtag_broadcast_cluster $jtag_broadcast_cluster -partial_mbist_central_comp $partial_mbist_central_comp -full_test_final_me_override $full_test_final_me_override -set_wr_inh $set_wr_inh_final -prgm_ram_ctl $prgm_ram_ctl -dummy_mbist_en $dummy_mbist_en -rdpath_x_clear_seq $rdpath_x_clear_seq -expect_lfsr_0 $expect_lfsr_0 -skip_chkbd_rd $skip_chkbd_rd -mbist_assertion $mbist_assertion -stagger_programming_cycle $stagger_programming_cycle -split_programming $split_programming -set_top_fs $set_top_fs -number_of_splits $number_of_splits -run_number $run_number -clear_serial_shift $clear_serial_shift -marker_suffix $marker_suffix -ist_clk_freq $ist_clk_freq -mask_all_rams $mask_all_rams -FA_shift_out $FA_shift_out -stop_on_first_error $stop_on_first_error

set clear_mbist_toggle 1
}
}
}
}

####only for mbist_step_mode verification test
if {([regexp {mbist_step_mode} $subtest] && ![regexp {initialization} $subtest] && ($rams_to_be_run == 1)) } {
tn_msg_clear_disabled_messages
if {($gen_emulation_vec == 1) } {
if { ($repairable == 1) } {
if {$subtest eq "mbist_step_mode_1"} {
set err_file "firstAddr_firstRam_rd55"
set initMe 45
set finalMe 47
set actualFailCM 2
} elseif {$subtest eq "mbist_step_mode_2"} {
set err_file "firstAddr_firstRam_rdaa"
set initMe 45
set finalMe 47
set actualFailCM 0
} elseif {$subtest eq "mbist_step_mode_3"} {
set err_file "lastAddr_lastRam_rd55"
set initMe 39
set finalMe 41
set actualFailCM 2
} elseif {$subtest eq "mbist_step_mode_4"} {
set err_file "lastAddr_lastRam_rdaa"
set initMe 39
set finalMe 41
set actualFailCM 0
} elseif {$subtest eq "mbist_step_mode_5"} {
set err_file "randomAddr_randomRam"
set initMe 56
set finalMe 56
set actualFailCM 0
}
set errFile "err_inj_stepping_${err_file}.tn"
source $errFile
set err_list [get_err_list_STUCK0_random]
set NoRst 0
foreach err $err_list {
set clusterId [lindex $err 0]
if {([llength $cluster_list] > 0) && ([lsearch -exact $cluster_list $clusterId] == -1)} {
continue
}

set regionId [lindex $err 1]
set domain_id [lindex $err 2]
set be_id [lindex $err 3]
set r_id [lindex $err 4]
set err_cols [lindex $err 5]
set address [lindex $err 6]
puts "INFO_MBIST: MBIST Actual error injected on c=$clusterId r=$regionId d=$domain_id, ram_id : $r_id , address = $address initMe =$initMe f =$finalMe -currMe $actualFailCM "
set clusterName [[lindex $jtagConfigList $clusterId] controller_type]
regsub {_clstr$} $clusterName {} clusterName
set region_inst [socf_get_region_inst $domainsXml $clusterName $regionId]
#puts "INFO_MBIST: MBIST reported fail will be on ram_id: $failing_ram_id fail address: $failAdr failCurrMe : $currMe failMe: $failMe"
set args_new [list -prgmConfig $prgmConfig -testConfig $testConfig -chipletId $clusterId -regionId $regionId -domainId $domain_id -beId $be_id -ramId $r_id -initMe $initMe -finalMe $finalMe -NoRst $NoRst -pll_freq_list $pll_freq_list -step_mode_subtest $subtest -use_read_ram $use_read_ram -debug_mode_wr_inh 1 -jtag_broadcast_cluster $jtag_broadcast_cluster -jtag_broadcast_client $jtag_broadcast_client -domainMaskList $domainMaskList -ist_mode_mbist $ist_mode_mbist -region_inst $region_inst -actualFailCM $actualFailCM -actual_fail_addr $address]
socf_mbist_step_mode args_new
set NoRst 1

}
}

} elseif {![$prgmConfig get_dry_run_mode]} {
puts "INFO_MBIST: Moving to RTI state "
jtag_init_to_state $jtagConfig RTI
waitRti $jtagConfig 10

tn_msg_clear_disabled_messages

## only for ate verification
set failed_tags_list [[$prgmConfig get_jtag_config ] get_failed_tag_list]
set failed_tags ""
puts "INFO_MBIST: DEBUG: starting cycle for for r=$repairable is $starting_cycle"
for {set i 0} {$i<[llength $failed_tags_list]} {incr i} {
set cycle_number [lindex $failed_tags_list $i]
if {$cycle_number > $starting_cycle} {
set failed_tags [concat $failed_tags [lindex $failed_tags_list [expr $i + 1] ]]
#puts "INFO_MBIST: f=$failed_tags"
}
incr i
}

set failedTagConfig [config_new_map]
config_set $failedTagConfig "failed_tags" "$failed_tags"
set pid [pid]
$prgmConfig set_property auto_broadcast force_disable
$prgmConfig set_program_value ".*/CHIP_BROADCAST_WRITE" ".*" -value 0
$prgmConfig set_program_value ".*/I1500_CHAIN_CTRL" ".*" -value 0
$prgmConfig program

set failed_tags_fn "failed_tags_1_${chiplet_inst}_${subtest}_${pid}_${repairable}.yml"
config_write_yaml $failedTagConfig $failed_tags_fn
set input_fail_rams_yaml "failed_tags_2_${chiplet_inst}_${subtest}_${pid}_${repairable}.yml"
set i 0

if {$pid_failed_yaml eq ""} {
uplevel #0 "exec /home/scratch.rkumari_gm108/nvtools_1/nvtools/ate/scripts/list_failing_rams_from_tags.pl -input_yaml failed_tags_1_${chiplet_inst}_${subtest}_${pid}_${repairable}.yml -verification 1 -output_yaml_file $input_fail_rams_yaml "
} else {
set input_fail_rams_yaml $pid_failed_yaml
}
set NoRst 0
set failedTag [config_read_yaml "$input_fail_rams_yaml"]
foreach chipletInst [config_map_keys $failedTag] {
set chipletInst_hash [config_map_value $failedTag $chipletInst]
foreach regionInst [config_map_keys $chipletInst_hash] {
set regionInst_hash [config_map_value $chipletInst_hash $regionInst]
foreach domainId [config_map_keys $regionInst_hash] {
set domainId_hash [config_map_value $regionInst_hash $domainId]
foreach bist_engine_id [config_map_keys $domainId_hash] {
if {($bist_engine_id eq "failing_me") || ($bist_engine_id eq "curr_me") } {
continue;
}
set bist_engine_hash [config_map_value $domainId_hash $bist_engine_id ]
foreach ramInst [config_map_keys $bist_engine_hash] {
if {($ramInst == "addr_base_bits") || ($ramInst == "ram_related_fail_tags") || ($ramInst eq "failing_ram_id") || ($ramInst eq "unrepairable_bist_engine") || $ramInst eq ("mbist_id") || ($ramInst eq "failure_in_mbist_top")} {
continue
}
set ramInst_hash [config_map_value $bist_engine_hash $ramInst]
set chipletId [config_map_value $ramInst_hash "chipletId"]
set mbist_id [config_map_value $ramInst_hash "mbist_id"]
set failing_ram_id [config_map_value $ramInst_hash "failing_ram_id"]
set regionId [config_map_value $ramInst_hash "regionId"]
set failMe [config_list [config_map_value $domainId_hash "failing_me"]]
set currMe [config_map_value $domainId_hash "curr_me"]
set failAdr [config_map_value $bist_engine_hash "addr_base_bits"]
puts "INFO_MBIST: DBG STEP_MODE : MBIST Running mbist_step_mode test for following RAM - $i chipletId $chipletId regionId = $regionInst domainId=$domainId bist_engine_id=$bist_engine_id r= $ramInst chipletId = $chipletId m=$failing_ram_id r=$regionId f=$failMe c=$currMe f=$failAdr. Start..."
set args_new [list -prgmConfig $prgmConfig -testConfig $testConfig -chipletId $chipletId -regionId $regionId -domainId $domainId -beId $bist_engine_id -ramId $failing_ram_id -failMe $failMe -currMe $currMe -failAdr $failAdr -NoRst $NoRst -pll_freq_list $pll_freq_list -step_mode_subtest $subtest -use_read_ram $use_read_ram -debug_mode_wr_inh 1 -jtag_broadcast_cluster $jtag_broadcast_cluster -jtag_broadcast_client $jtag_broadcast_client -region_inst $regionInst -domainMaskList $domainMaskList -ist_mode_mbist $ist_mode_mbist]
socf_mbist_step_mode args_new
set NoRst 1
puts "INFO_MBIST: Moving to RTI state "
puts "INFO_MBIST : completed running for RAM# $i r=$ramInst"
jtag_init_to_state $jtagConfig RTI
waitRti $jtagConfig 10
incr i
}
}
}
}
}
}

}

puts "INFO_MBIST: Moving to RTI state "
jtag_init_to_state $jtagConfig RTI
waitRti $jtagConfig 10

}

proc simple_ist_test { args } {
set orig_args $args
global testConfig

set options {
{svop.arg 00 "-svop"}
{prgmConfig.arg "" "-prgmConfig object" "NO_CUSTOMIZE"}
{testConfig.arg "" "<test config object>" "NO_CUSTOMIZE"}
{cluster_list.arg "" "-list of clusters to be run"}
{fs_group_list.arg "" "-fs region grouping for IST"}
{ListArgs.arg "" "-option helper"}

}

array set params [::cmdline::getKnownOptions args $options ]
if { $params(ListArgs) != "" } {
upvar $params(ListArgs) fullopt
set options "$fullopt $options"
set fullopt $options
::ATE::AteFlowUtils::setTestApiProperty -name_of_list fullopt -categoryName execution_ctrl -propName chiplet_flow_certified -value 1
::ATE::AteFlowUtils::setTestApiProperty -name_of_list options -categoryName "execution_ctrl" -propName "test_type" -value "RAM_TEST"
::ATE::AteFlowUtils::setTestApiProperty -name_of_list options -categoryName "execution_ctrl" -propName "dft_mode" -value "MBIST"
::ATE::AteFlowUtils::setTestApiProperty -name_of_list fullopt -categoryName "execution_ctrl" -propName "test_features" -value "secSHA2 mbist ramctl mbistFS"
return
}

if { $params(ListArgs) == "" } {
set prgmConfig $params(prgmConfig)
set svop $params(svop)
set testConfig $params(testConfig)
set cluster_list $params(cluster_list)
}
#puts "::IST::JTAGSEQ_START::mbist_cfg::"
#puts "::IST::JTAGSEQ_END::mbist_cfg::"
puts "::IST::JTAGSEQ_START::mbist_trgr::"

$prgmConfig set_property single_controller_per_shift "force_enable";
if {$cluster_list == ""} {
$prgmConfig set_program_value ".*/I1500_CHAIN_CTRL" ".*partition_byp.*" -value 1'b0
$prgmConfig set_program_value ".*/I1500_CHAIN_CTRL" ".*broadcast_write.*" -value 1'b1
$prgmConfig program -noAutoBroadcast
} else {
foreach cluster $cluster_list {
$prgmConfig set_program_value ".*${cluster}.*/I1500_CHAIN_CTRL" ".*partition_byp.*" -value 1'b0
$prgmConfig set_program_value ".*${cluster}.*/I1500_CHAIN_CTRL" ".*broadcast_write.*" -value 1'b1
$prgmConfig program -noAutoBroadcast
}
$prgmConfig set_program_value ".*CHIP_BROADCAST_WRITE" ".*cluster_byp.*" -value 1'b1
foreach cluster $cluster_list {
$prgmConfig set_program_value ".*${cluster}.*CHIP_BROADCAST_WRITE" ".*cluster_byp.*" -value 1'b0
}
}
$prgmConfig set_property single_controller_per_shift "force_disable";
$prgmConfig set_program_value ".*CHIP_BROADCAST_WRITE" ".*cluster_byp.*" -value 1'b1

foreach cluster $cluster_list {
$prgmConfig set_program_value ".*${cluster}.*CHIP_BROADCAST_WRITE" ".*cluster_byp.*" -value 1'b0
}
$prgmConfig set_program_value ".*CHIP_BROADCAST_WRITE" ".*broadcast_write.*" -value 1'b1
$prgmConfig program -noAutoBroadcast
if {$cluster_list == ""} {
$prgmConfig set_program_value ".*/MBIST_TOP" ".*start_bits.*" -value 1'b1
$prgmConfig set_program_value ".*/MBIST_TOP" ".*enable_bist_bits.*" -value 1'b1
$prgmConfig program
} else {
foreach cluster $cluster_list {
$prgmConfig set_program_value ".*${cluster}.*MBIST_TOP" ".*start_bits" -value 1'b1
$prgmConfig set_program_value ".*${cluster}.*MBIST_TOP" ".*enable_bist_bits" -value 1'b1
}
$prgmConfig program
}
puts "::IST::JTAGSEQ_END::mbist_trgr::"
puts "::IST::JTAGSEQ_START::mbist_sts::"

###set expected value
$prgmConfig set_program_value ".*CHIP_BROADCAST_WRITE" ".*cluster_byp.*" -value 1'b1
foreach cluster $cluster_list {
$prgmConfig set_program_value ".*${cluster}.*CHIP_BROADCAST_WRITE" ".*cluster_byp.*" -value 1'b0
}
$prgmConfig set_program_value ".*CHIP_BROADCAST_WRITE" ".*broadcast_write.*" -value 1'b0
$prgmConfig program -noAutoBroadcast

$prgmConfig set_property single_controller_per_shift "force_enable";
$prgmConfig set_program_value ".*/I1500_CHAIN_CTRL" ".*partition_byp.*" -value 1'b0
$prgmConfig set_program_value ".*/I1500_CHAIN_CTRL" ".*broadcast_write.*" -value 1'b0
$prgmConfig program -noAutoBroadcast

if {$cluster_list == ""} {
$prgmConfig set_program_value ".*/MBIST_TOP" ".*start_bits.*" -expected 1'b1
$prgmConfig set_program_value ".*MBIST_TOP" ".*enable_bist_bits" -expected 1'b1
$prgmConfig program -noAutoBroadcast
} else {
foreach cluster $cluster_list {
$prgmConfig set_program_value ".*${cluster}.*MBIST_TOP" ".*start_bits" -expected 1'b1
$prgmConfig set_program_value ".*${cluster}.*MBIST_TOP" ".*enable_bist_bits" -expected 1'b1
$prgmConfig program -noAutoBroadcast

}
}
puts "::IST::JTAGSEQ_END::mbist_sts::"

###clearing out registers
puts "::IST::JTAGSEQ_START::mbist_clr::"

$prgmConfig set_property single_controller_per_shift "force_enable";
if {$cluster_list == ""} {
$prgmConfig set_program_value ".*/I1500_CHAIN_CTRL" ".*partition_byp.*" -value 1'b0
$prgmConfig set_program_value ".*/I1500_CHAIN_CTRL" ".*broadcast_write.*" -value 1'b1
$prgmConfig program -noAutoBroadcast
} else {
foreach cluster $cluster_list {
$prgmConfig set_program_value ".*${cluster}.*/I1500_CHAIN_CTRL" ".*partition_byp.*" -value 1'b0
$prgmConfig set_program_value ".*${cluster}.*/I1500_CHAIN_CTRL" ".*broadcast_write.*" -value 1'b1
$prgmConfig program -noAutoBroadcast
}
$prgmConfig set_program_value ".*CHIP_BROADCAST_WRITE" ".*cluster_byp.*" -value 1'b1
foreach cluster $cluster_list {
$prgmConfig set_program_value ".*${cluster}.*CHIP_BROADCAST_WRITE" ".*cluster_byp.*" -value 1'b0
}
}
$prgmConfig set_property single_controller_per_shift "force_disable";

$prgmConfig set_program_value ".*CHIP_BROADCAST_WRITE" ".*broadcast_write.*" -value 1'b1
$prgmConfig program -noAutoBroadcast

if {$cluster_list == ""} {
$prgmConfig set_program_value ".*/MBIST_TOP" ".*" -value 1'b0 -replicate
$prgmConfig program
} else {
foreach cluster $cluster_list {
$prgmConfig set_program_value ".*${cluster}.*/MBIST_TOP" ".*" -value 1'b0 -replicate

}
$prgmConfig program
}
$prgmConfig set_program_value ".*CHIP_BROADCAST_WRITE" ".*cluster_byp.*" -value 1'b0
$prgmConfig set_program_value ".*CHIP_BROADCAST_WRITE" ".*broadcast_write.*" -value 1'b0
$prgmConfig program -noAutoBroadcast

$prgmConfig set_property single_controller_per_shift "force_enable";
$prgmConfig set_program_value ".*/I1500_CHAIN_CTRL" ".*partition_byp.*" -value 1'b0
$prgmConfig set_program_value ".*/I1500_CHAIN_CTRL" ".*broadcast_write.*" -value 1'b0
$prgmConfig program -noAutoBroadcast
puts "::IST::JTAGSEQ_END::mbist_clr::"

}

proc socf_prog_mbist_interface { args_ref } {
upvar $args_ref args
set orig_args $args
global domainsXml

set options {
{svop.arg 00 "-svop"}
{prgmConfig.arg "" "-prgmConfig object" "NO_CUSTOMIZE"}
{testConfig.arg "" "<test config object>" "NO_CUSTOMIZE"}
{domainMaskList.arg "[list]" "-list of domains to be masked. Usage : -domainMaskList '{{<1st region_id> {<list of masked domain id>}} ... {<Nth region_id> {<list of masked domain id>}}}'"}
{regionMaskList.arg "[list]" "-list of regions to be masked"}
{region_inst.arg "ALL_REGION" "-targeted region"}
{regionId.arg "-1" "-targeted region"}
{chipletId.arg "-1" "-targeted chiplet"}
{marchElemList.arg "" "-list of march elements"}
{waitCycles.arg 500 "-default waitCycles between writes and reads"}
{bist_on.arg "0" "-keep mbist_en asserted at end of the end"}
{diag_en.arg "3" "-diag_en controls the level of diagnostic detail in prog bist test"}
{ramList.arg "" "-list of rams to be masked while running test"}
{enableFlag.arg "0" "-flag that enables or disables the list of rams to be targeted"}
{waitcycle_override.arg 0 ""}
{pll_freq_list.arg "" "path of pll_freq_list"}
{testConfig.arg "" "testConfig object"}
{use_be_id.arg "1" "-decide the format to be used for ramlist"}
{Ram_UnMask.arg "None" "specify type of ram to be Unmasked"}
{Ram_Mask.arg "None" "specify type of ram to be Masked"}
{Clk_UnMask.arg "None" "specify clock domain which need to be Unmasked"}
{Clk_Mask.arg "None" "specify clock domain which need to be Masked"}
{err_inj_mode.arg "" "Specify mode of selfchk"}
{err_inj_mode.arg "" "Specify mode of selfchk"}
{lpc_prog_on.arg "1" "by default lpc programming will be enabled in chip having lpc inseterd mbist"}
{ctrl_chain_mode.arg "broadcast_mbist_ctrl_chain" "disable broadcast mode in for ctrl chain gv100 onward"}
{host_chain_mode.arg "mbist_hostaccess_chain" "shift local status chain indaisy mode gv100 onward"}
{status_chain_mode.arg "daisy_mbist_status_chain" "shift local control chain shift in in daisy mode gv100 onward"}
{jtag_broadcast_client.arg "1" "use jtag broadcast for clients wherever possible"}
{jtag_broadcast_cluster.arg "0" "use jtag broadcast for cluster wherever possible"}
{full_test_final_me_override.arg "0" "used for pickingup ull test FinalMe from full_test_finalme_override key"}
{ist_mode_mbist.arg "0" "-enable IST mode"}
{no_ist_seq_markers.arg "0" "-remove sequence markers in ist_mode"}
{last_seq_mbistwait.arg "0" "-mbist wait will be the last seq"}
{cfg_access_latency.arg "" "program access latency in Rams which have this feature"}
{cfg_rdata_pipeline.arg "" "program rd data pipeline"}
{toggle_rst.arg "0" "toggling mbist_ramacces_rst_ after getting mbist_en high"}
{dummy_mbist_en.arg "1" "set mbist_en high before setting enable_bist"}
{debug_mode_wr_inh.arg "0" "toggle debug_mode during debug_mode toggling"}
{cluster_list.arg "" "-list of clusters to be run"}
{shift_addr_bits.arg "" "-value for addr_base programming"}
{hi_addr.arg "" "high address"}
{low_addr.arg "" "low address"}
{hi_me.arg "" "high me"}
{low_me.arg "" "low me"}
{loop_en.arg "0" "loop enable"}
{subtest.arg "" "Type of test"}
{NoRst.arg "0" "-NoRst"}
{clear_mbist_toggle.arg "0" "toggle clear_mbist at the beginning"}
{set_wr_inh.arg "1" "set RAM_CTL wr_inh bit to 1"}
{enable_crc_dump.arg "-1" "option to enable crc dump"}
{enable_crc_cmp.arg "-1" "option to enable crc compare"}

{ListArgs.arg "" "-option helper"}
}

array set params [::cmdline::getKnownOptions args $options ]
if { $params(ListArgs) != "" } {
upvar $params(ListArgs) fullopt
set options "$fullopt $options"
set fullopt $options
return
} else {
# parray params
# puts "INFO_MBIST: remain args: $args"
}

if { $params(ListArgs) == "" } {
set prgmConfig $params(prgmConfig)
set jtagConfig [$prgmConfig get_jtag_config]
set testConfig $params(testConfig)
set domainMaskList $params(domainMaskList)
set marchElemList $params(marchElemList)
set regionMaskList $params(regionMaskList)
set region_inst $params(region_inst)
set wait_time $params(waitCycles)
set bist_on $params(bist_on)
set svop $params(svop)
set diag_en $params(diag_en)
set ramList $params(ramList)
set subtest $params(subtest)
set enableFlag $params(enableFlag)
set pll_freq_list $params(pll_freq_list)
set waitcycle_override $params(waitcycle_override)
set testConfig $params(testConfig)
set jtagConfigList [jtag_config_list $jtagConfig]
set chipletId $params(chipletId)
set Ram_UnMask $params(Ram_UnMask)
set Ram_Mask $params(Ram_Mask)
set Clk_UnMask $params(Clk_UnMask)
set Clk_Mask $params(Clk_Mask)
set err_inj_mode $params(err_inj_mode)
set lpc_prog_on $params(lpc_prog_on)
set ctrl_chain_mode $params(ctrl_chain_mode)
set host_chain_mode $params(host_chain_mode)
set status_chain_mode $params(status_chain_mode)
set jtag_broadcast_client $params(jtag_broadcast_client)
set jtag_broadcast_cluster $params(jtag_broadcast_cluster)
set full_test_final_me_override $params(full_test_final_me_override)
set ist_mode_mbist $params(ist_mode_mbist)
set last_seq_mbistwait $params(last_seq_mbistwait)
set no_ist_seq_markers $params(no_ist_seq_markers)
set cfg_access_latency $params(cfg_access_latency)
set cfg_rdata_pipeline $params(cfg_rdata_pipeline)
set toggle_rst $params(toggle_rst)
set dummy_mbist_en $params(dummy_mbist_en)
set debug_mode_wr_inh $params(debug_mode_wr_inh)
set cluster_list $params(cluster_list)
set hi_addr $params(hi_addr)
set low_addr $params(low_addr)
set hi_me $params(hi_me)
set low_me $params(low_me)
set loop_en $params(loop_en)
set use_be_id $params(use_be_id)
set shift_addr_bits $params(shift_addr_bits)
set clear_mbist_toggle $params(clear_mbist_toggle)
set NoRst $params(NoRst)
set set_wr_inh $params(set_wr_inh)
set enable_crc_dump $params(enable_crc_dump)
set enable_crc_cmp $params(enable_crc_cmp)

if { [config_map_value [config_find $testConfig CURRENT_TEST] design_scope] == "FULLCHIP" } {
if { $chipletId != -1 } {
set chiplet_hier_inst [socf_get_chiplet_inst $jtagConfigList $chipletId]
set configIndex $chipletId
set chiplet_inst [[lindex $jtagConfigList $configIndex] controller_type]
regsub {_clstr$} $chiplet_inst {} chiplet_inst
} else {
set chiplet_inst "FULLCHIP"
set configIndex [chipletInst_to_configIndex $jtagConfigList $chiplet_inst $domainsXml]
}
} else {
set chiplet_inst [config_map_value [config_find $testConfig CURRENT_TEST] design_scope]
set configIndex [chipletInst_to_configIndex $jtagConfigList $chiplet_inst $domainsXml]
}
# set chiplet_inst [config_map_value [config_find $testConfig CURRENT_TEST] design_scope]
# set configIndex [chipletInst_to_configIndex $jtagConfigList $chiplet_inst $domainsXml]
set regionId $params(regionId)
set regionConfig [config_map_value $domainsXml "region_list"]
if { $regionId != -1 } { set region_inst [socf_get_region_inst $domainsXml $chiplet_inst $regionId] }
if {[config_has_key $regionConfig "pseudo_clust_inst" ]} {
set temp [config_list [config_find $testConfig CURRENT_TEST/CURRENT_SUBTEST/TESTSCRIPT_DEFINED_ARGS/chiplet_name] ]
regsub {_cli$} $temp {} temp
set temp [string tolower $temp]
# append temp2 $temp "_cli_inst"
set region_inst $temp
}

set design_type [config_map_value [config_find $testConfig CURRENT_TEST] design_type]

set clock_mode [config_map_value [config_find $testConfig CURRENT_TEST] clock_mode]

if {$err_inj_mode == 1} {
set err_inj_type "firstAddr_firstCol"
} elseif {$err_inj_mode == 2} {
set err_inj_type "secondAddr_lastCol"
} elseif {$err_inj_mode == 3} {
set err_inj_type "firstSecondAddr_firstLastCol"
} else {
set err_inj_type ""
}

socf_prog_bist $prgmConfig $jtagConfigList $configIndex $domainsXml {} $wait_time $marchElemList -chiplet_inst $chiplet_inst -regionMaskList $regionMaskList -subtest $subtest -domainMaskList $domainMaskList -bist_on $bist_on -diag_en $diag_en -oneShift 1 -design_type $design_type -clock_mode $clock_mode -waitcycle_override $waitcycle_override -pll_freq_list $pll_freq_list -testConfig $testConfig -region_inst $region_inst -svop $svop -err_inj_type $err_inj_type -lpc_prog_on $lpc_prog_on -ctrl_chain_mode $ctrl_chain_mode -host_chain_mode $host_chain_mode -status_chain_mode $status_chain_mode -debug_mode_wr_inh $debug_mode_wr_inh -jtag_broadcast_client $jtag_broadcast_client -jtag_broadcast_cluster $jtag_broadcast_cluster -dummy_mbist_en $dummy_mbist_en -toggle_rst $toggle_rst -ist_mode_mbist $ist_mode_mbist -no_ist_seq_markers $no_ist_seq_markers -last_seq_mbistwait $last_seq_mbistwait -cfg_access_latency $cfg_access_latency -cfg_rdata_pipeline $cfg_rdata_pipeline -cluster_list $cluster_list -hi_addr $hi_addr -low_addr $low_addr -hi_me $hi_me -low_me $low_me -loop_en $loop_en -ramList $ramList -use_be_id $use_be_id -shift_addr_bits $shift_addr_bits -clear_mbist_toggle $clear_mbist_toggle -NoRst $NoRst -set_wr_inh $set_wr_inh -enableFlag $enableFlag -enable_crc_dump $enable_crc_dump -enable_crc_cmp $enable_crc_cmp

}
}

proc socf_prog_mbist_error_interface { args_ref } {
upvar $args_ref args
set orig_args $args
global domainsXml

# Default marchElemList is : "{wr11, incr_addr} {rd11, incr_addr}" (same as current baseTest me[37] , me[38])
set options {
{svop.arg 00 "-svop"}
{prgmConfig.arg "" "-prgmConfig object" "NO_CUSTOMIZE"}
{testConfig.arg "" "<test config object>" "NO_CUSTOMIZE"}
{domainMaskList.arg "[list]" "-list of domains to be masked. Usage : -domainMaskList '{{<1st region_id> {<list of masked domain id>}} ... {<Nth region_id> {<list of masked domain id>}}}'"}
{marchElemList.arg "" "-list of march elements"}
{regionMaskList.arg "[list]" "-list of regions to be masked"}
{waitCycles.arg 500 "-default waitCycles between writes and reads"}
{bist_on.arg "0" "-keep mbist_en asserted at end of the end"}
{diag_en.arg "3" "-diag_en controls the level of diagnostic detail in prog bist test"}
{ramList.arg "[list]" "-list of rams to be masked while running test"}
{enableFlag.arg "0" "-flag that enables or disables the list of rams to be targeted"}
{use_be_id.arg "0" "-decide the format to be used for ramlist"}
{repairFlag.arg "0" "-flag that enables or disables fuse repair of rams"}
{stuckFault.arg "0" "-stuck fault injected"}
{faultAddress.arg "" "-address at which fault is injected"}
{errFile.arg "" "-error list"}
{waitcycle_override.arg "0" "overrides internal calculated wait cycles"}
{pll_freq_list.arg "" "list of pll clock frequencies to calculte wait cycles"}
{blocksXml.arg "" "path of blocksXml file describing memroy subarray details"}
{mask_unrepariable_domain.arg "1" "make it 0 if want to run test on all mbist domains"}
{region_inst.arg "ALL_REGION" "-targeted region"}
{regionId.arg "-1" "-targeted region"}
{err_inj_type.arg "" "ERR INJ Type"}
{chipletId.arg "-1" "-targeted chiplet"}
{loop_en.arg "" "setting to enable loop_mode"}
{subtest.arg "" "Type of test"}
{progbist_type.arg "" "Type of progbist test. eg. Multi"}
{verify_ram_mask.arg "0" "Set 1 to verify ram masking using ram mask list present in err list tn file"}
{verify_hi_low_addr.arg "0" "Set 1 to verify high_addr/lo_addr using the values present in err list tn file"}
{NoRst.arg "0" "-NoRst"}
{lpc_prog_on.arg "1" "by default lpc programming will be enabled in chip having lpc inseterd mbist"}
{ctrl_chain_mode.arg "broadcast_mbist_ctrl_chain" "disable broadcast mode in for ctrl chain gv100 onward"}
{host_chain_mode.arg "mbist_hostaccess_chain" "shift local status chain indaisy mode gv100 onward"}
{status_chain_mode.arg "daisy_mbist_status_chain" "shift local control chain shift in in daisy mode gv100 onward"}
{jtag_broadcast_client.arg "1" "use jtag broadcast for clients wherever possible"}
{jtag_broadcast_cluster.arg "0" "use jtag broadcast for cluster wherever possible"}
{full_test_final_me_override.arg "0" "used for pickingup ull test FinalMe from full_test_finalme_override key"}
{ist_mode_mbist.arg "0" "-enable IST mode"}
{no_ist_seq_markers.arg "0" "-remove sequence markers in ist_mode"}
{last_seq_mbistwait.arg "0" "-mbist wait will be the last seq"}
{cfg_access_latency.arg "" "program access latency in Rams which have this feature"}
{cfg_rdata_pipeline.arg "" "program rd data pipeline"}
{toggle_rst.arg "0" "toggling mbist_ramacces_rst_ after getting mbist_en high"}
{dummy_mbist_en.arg "1" "set mbist_en high before setting enable_bist"}
{debug_mode_wr_inh.arg "0" "toggle debug_mode during debug_mode toggling"}
{cluster_list.arg "" "-list of clusters to be run"}
{prgm_ram_ctl.arg "1" "clear RAM_CTL in the begining"}
{ListArgs.arg "" "-option helper"}
}

array set params [::cmdline::getKnownOptions args $options ]
if { $params(ListArgs) != "" } {
upvar $params(ListArgs) fullopt
set options "$fullopt $options"
set fullopt $options
return
} else {
# parray params
# puts "INFO_MBIST: remain args: $args"
}

if { $params(ListArgs) == "" } {
set prgmConfig $params(prgmConfig)
set jtagConfig [$prgmConfig get_jtag_config]
set jtagConfigList [jtag_config_list $jtagConfig]
set testConfig $params(testConfig)
set domainMaskList $params(domainMaskList)
set marchElemList $params(marchElemList)
set regionMaskList $params(regionMaskList)
set wait_time $params(waitCycles)
set bist_on $params(bist_on)
set diag_en $params(diag_en)
set ramList $params(ramList)
set enableFlag $params(enableFlag)
set use_be_id $params(use_be_id)
set repairFlag $params(repairFlag)
set stuckFault $params(stuckFault)
set svop $params(svop)
set faultAddress $params(faultAddress)
set errFile $params(errFile)
set waitcycle_override $params(waitcycle_override)
set pll_freq_list $params(pll_freq_list)
set blocksXmlFile $params(blocksXml)
set region_inst $params(region_inst)
set chipletId $params(chipletId)
set mask_unrepariable_domain $params(mask_unrepariable_domain)
set err_inj_type $params(err_inj_type)
set subtest $params(subtest)
set progbist_type $params(progbist_type)
set verify_hi_low_addr $params(verify_hi_low_addr)
set verify_ram_mask $params(verify_ram_mask)
set NoRst $params(NoRst)
set lpc_prog_on $params(lpc_prog_on)
set ctrl_chain_mode $params(ctrl_chain_mode)
set host_chain_mode $params(host_chain_mode)
set status_chain_mode $params(status_chain_mode)
set jtag_broadcast_client $params(jtag_broadcast_client)
set jtag_broadcast_cluster $params(jtag_broadcast_cluster)
set full_test_final_me_override $params(full_test_final_me_override)
set ist_mode_mbist $params(ist_mode_mbist)
set last_seq_mbistwait $params(last_seq_mbistwait)
set no_ist_seq_markers $params(no_ist_seq_markers)
set cfg_access_latency $params(cfg_access_latency)
set cfg_rdata_pipeline $params(cfg_rdata_pipeline)
set toggle_rst $params(toggle_rst)
set dummy_mbist_en $params(dummy_mbist_en)
set debug_mode_wr_inh $params(debug_mode_wr_inh)
set cluster_list $params(cluster_list)
set prgm_ram_ctl $params(prgm_ram_ctl)
if {$params(loop_en) != ""} {
set loop_en $params(loop_en)
} elseif {($progbist_type == "Multi") && ($verify_hi_low_addr == 0) && ($verify_ram_mask == 0)} {
set loop_en 1
} else {
set loop_en 0
}

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